EMC and Shared SRAM/FLASH Bus

Hi,

I'm a student new to fpga design and am trying to design a board with a
spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld;
all sharing a common address/data bus.  I'm interested in accomplishing
the following:

1.  The ability to configure the spartan-3 from FLASH using the CPLD.
2.  Access to SRAM, FLASH, and a few memory mapped cpld registers using
the Xilinx EDK/EMC core.

My confusion is with regards to how the address bus should be connected
to the FLASH and SRAM's.  The design's I have seen seem to connect the
FLASH A0 to A1 or A2 of the FPGA address bus.  Similarly the RAM is
then connected to A2.  My suspsion is that this is related to the data
width of each device or the size of the data that is allowed to be
written?  I should note that my SRAM's are being used as a single
32b-wide memory and the FLASH and CPLD are only 16b wide.  Anyway if
someone could clarify the issue it would be much appreciated.

Matt

"Matt" <mhilt1@binghamton.edu> schrieb im Newsbeitrag
news:1108831530.424417.75300@z14g2000cwz.googlegroups.com...
> Hi,
>
> I'm a student new to fpga design and am trying to design a board with a
> spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld;
> all sharing a common address/data bus.  I'm interested in accomplishing
> the following:
>
> 1.  The ability to configure the spartan-3 from FLASH using the CPLD.

there are several appnotes with hdl source for this

> 2.  Access to SRAM, FLASH, and a few memory mapped cpld registers using
> the Xilinx EDK/EMC core.
its doable

> My confusion is with regards to how the address bus should be connected
> to the FLASH and SRAM's.  The design's I have seen seem to connect the
> FLASH A0 to A1 or A2 of the FPGA address bus.  Similarly the RAM is
> then connected to A2.  My suspsion is that this is related to the data
> width of each device or the size of the data that is allowed to be
> written?  I should note that my SRAM's are being used as a single
> 32b-wide memory and the FLASH and CPLD are only 16b wide.  Anyway if
> someone could clarify the issue it would be much appreciated.
>
> Matt

the EDK bus-bit ordering IS confusing, in most cases it causes problem
at first trial attempt. Also note that the EMC core has a bug when using
Flash that is not 32 bit wide the bus-widht matching logic generates
2 CEn pulses per 16bit memory access to additional logic that filters
the second pulse out is required if you want to program the flash from
the microblaze

Antti

Thanks for the reply.  I think however that my concern at this point is
less with the EMC and more with how the address signals should be
connected on the board.  Should the address bus look like:

Flash_A0 --- SRAM_A0 --- FPGA
Flash_A1 --- SRAM_A1 --- FPGA
Flash_A2 --- SRAM_A2 --- FPGA ...

or ( as I've seen it elsewhere)

Flash_A0 --- FPGA
Flash_A1 --- SRAM_A0 --- FPGA
Flash_A2 --- SRAM_A1 --- FPGA ...

Matt

"Matt" <mhilt1@binghamton.edu> wrote in message 
news:1108840197.634046.211860@l41g2000cwc.googlegroups.com...
> Thanks for the reply.  I think however that my concern at this point is
> less with the EMC and more with how the address signals should be
> connected on the board.  Should the address bus look like:
>
> Flash_A0 --- SRAM_A0 --- FPGA
> Flash_A1 --- SRAM_A1 --- FPGA
> Flash_A2 --- SRAM_A2 --- FPGA ...
>
> or ( as I've seen it elsewhere)
>
> Flash_A0 --- FPGA
> Flash_A1 --- SRAM_A0 --- FPGA
> Flash_A2 --- SRAM_A1 --- FPGA ...
>
> Matt
>

I really think that the answer requires reading the data sheet of the 
particular memory devices you want to use.

For two TH50VSF2881AASB 16 bit SRAM/FLASH devices for a Big Endian Bus, I 
have

FPGA_sram_addr<29>   AB_MemChip_A0
FPGA_sram_addr<28>   AB_MemChip_A1
.....
FPGA_sram_data<31>    B_MemChip_DQ0
FPGA_sram_data<30>    B_MemChip_DQ1
....
FPGA_sram_data<15>    A_MemChip_DQ0
FPGA_sram_data<14>    A_MemChip_DQ1
....
FPGA_sram_cen<0>        AB_MemChip_CE1SN
FPGA_sram_cen<1>        AB_MemChip_CEFN
FPGA_wen                       AB_MemChip_WEN
FPGA_oen                        AB_MemChip_OEN
FPGA_sram_ben<1>        A_MemChip_LBN
FPGA_sram_ben<0>        A_MemChip_UBN
FPGA_sram_ben<3>        B_MemChip_LBN
FPGA_sram_ben<2>        B_MemChip_UBN

I did this by hand, so there may be typo's

-Newman