Antti Lukats: all my past live projects to be published...

"Erik Widding" <widding@birger.com> schrieb im Newsbeitrag
news:1109017970.523487.109230@l41g2000cwc.googlegroups.com...
> > 1) for EDK the _I _O _T useage is required to be "EDK compliant" -
> this
> > issue has nothing todo with XST inout handling
>
> Actually EDK can handle tristate buffers declared inside of a pcore.
> The syntax for the MPD is as follows:
>
>    PORT AD               = "" , DIR=inout, VEC=[31:0], 3STATE=FALSE,
> IOB_STATE=BUF
>
> This exists because some IP is very tightly bound to its IO pin type,
> such as PCI or DDR SDRAM.  We requested this feature from Xilinx a few
> years ago specifically so that we could use the PCI logicore netlist
> inside of a wrapper in EDK, without hand editing the top level VHDL.
>
>
> Regards,
> Erik.

Hi Erik,

YES and NO.

EDK can work as described, YES.
but the IO buffers are NOT inside the PCI logicore netlist!
----------------------------------------------------------------------------
------------------
  XPCI_ADB0 : IOBUF_PCI33_3 port map
              ( O => AD_I0 , IO => AD_IO( 0), I => AD_O0 , T =>
_ADO_B   );
----------------------------------------------------------------------------
------------------
PCI IO buffers for Xilinx OPB PCI core are instantiated in the VHDL code
as can be seen above and NOT inside the PCI logicore netlist!

and as of DDR SDRAM core there the _I _O _T is used as normal

        DDR_DQ_o            =>  DDR_DQ_o            ,
        DDR_DQ_i            =>  DDR_DQ_i            ,
        DDR_DQ_t            =>  DDR_DQ_t            ,

Antti

> > This exists because some IP is very tightly bound to its IO pin
type,
> > such as PCI or DDR SDRAM.  We requested this feature from Xilinx a
few
> > years ago specifically so that we could use the PCI logicore
netlist
> > inside of a wrapper in EDK, without hand editing the top level
VHDL.
>
> YES and NO.
> EDK can work as described, YES.
> but the IO buffers are NOT inside the PCI logicore netlist!
> PCI IO buffers for Xilinx OPB PCI core are instantiated in the VHDL
code
> as can be seen above and NOT inside the PCI logicore netlist!
> and as of DDR SDRAM core there the _I _O _T is used as normal

I think you have missed the point.  I make absolutely no mention of EDK
IP.

First with respect to the PCI logicore, which if purchased from Xilinx
is provided with an EDF netlist, and a VHDL netlist (or as some would
say "structural VHDL") that instantiates this core netlist, the IO
pins, and a user configurable module.  To use this entire package,
without editing any of the IP core from the vendor, which is delivered
as both VHDL and a netlist, one must do as I described.  This still
requires some editing of the contraints that are provided by the
vendor, but only for location in the hierarchy.

Secondly, DDR SDRAM was cited as an example because separating out the
tristate buffer from the DDR register is counter to the architecture of
the FPGA.  The IO cell in virtex2 contatains a tristate buffer and a
DDR register, each of which only exist in this type of cell.  Breaking
off the tristate buffer from the DDR register does not provide for any
sort of meaningful improvement in the hierarchy.  Rather, it confuses
the issue.  Arguments for breaking the hierarchy at this point that
have been presented in this newsgroup are: using chipscope at the top
level of a hierarchy; or the creation of a vendor agnostic design.
Given that the signal between the DDR register and the OBUF, or the
IBUF and the other DDR register are not observable, as the wires simply
do not exist in the architecture, obviates the first argument.  The
fact that the DDR register and the IO buffer are both vendor specific,
and vendor unique, obviates the second argument.

As the FPGAs get more encompassing IO structures, as with V4, it makes
more and more sense to bind the IO structures which will include shift
register, differential pins, etc, into the cores themselves.  One is
kidding himself if he believes he can do a high performance and cost
effective design without expressly instantiating specific architectural
elements.  The IO structures are no exception.

This is not to say what Xilinx did with the EDK and separating out
tristates did not make sense.  It did, when specific IO pin types and
IO structures did not need to be called out from the underlying core.
For example, many people new to FPGAs and the coreconnect bus
architecture have started by using the GPIO module to interface to
their own IP inside the chip.  This is a good example of where one may
want to use the same IP for on chip or off chip interconnect, and as
such, not binding the IO pins to the core results in one rather than
two cores being created.



Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

 (mail) 100 Boylston St #1070; Boston, MA 02116
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