Hardcopy Vs ASIC

I was going through the hard copy product from altera. Methodology
seems really promising. I just wonder where hard copy products stands
as compare to ASIC wrt performance, power, yield & Time to market

Dig,

glad to hear you like the look of the methodology. Regarding your
question, then it rather depends on whether you are talking vs
standard-cell ASIC, or Structured ASIC. All Structured ASICs have a
larger die size and less ultimate performance than standard-cell ASICs.
However, they make up for this (for the majority of applications) by
offering much lower NREs, lower minimum order quantities, reduced risk
and better time-to-market. For the current version of HardCopy that is
shipping today (HardCopy Stratix - based on the same 0.13um process we
use for Stratix FPGAs), then the only really meaningful performance
figure I can give you is that we tend to find an average of 50% speed
up from the Stratix FPGA. We have seen typical system speeds over
150MHz, though with pipelining, you could achieve more. Power is lower
than the FPGA, typically 25-40% or so. Last month we announced the next
generation, HardCopy II, based on the same 90nm process we are using
for the Stratix II and Cyclone II FPGAs. This will increase performance
significantly, typically doubling what is possible on the FPGA. We
expect "real" system performance figures of 350MHz. Power will also be
lower and we expect core figures of 50-70% lower than the FPGA.

By yield, I assume you really mean cost. The die-size of any chip is of
course what dominates the cost and in the case of Structured ASICs such
as HardCopy, the die-size is larger than a fully optimised standard
cell ASIC. However, the NRE charge will significantly lower and you
therefore need to look at the total cost. For HardCopy Stratix, we tend
to find above volumes of 50K-100K, standard cell ASIC tends to work out
more cost effective, though we have seen some memorable exceptions
where customers have gone well over these volumes, usually because
time-to-market matters a lot more. Because HardCopy II is significantly
more die-size optimised, (and because ASIC NREs are continuing to
increase) we expect that the volumes at which break-even makes sense
will increase significantly, to somewhere between 250K-500K units per
year.

So coming to time-to-market, Structured ASICs in general are typically
far faster to market than standard cell ASICs, because so much of the
back-end work is already done. HardCopy is a lot faster than any other
structured ASIC because we guarantee the migration from a working FPGA
to the HardCopy device. The typical turnaround time to protos is 10
weeks, including the migration in our design center and the fab and
assembly time.

If you're interested in learning more and can spare 40 mins to an hour,
(and can forgive a blatant plug), we did a Net Seminar on this last
week which includes information on the latest version - HardCopy II.
You can look at it here. (Registration required)
http://cmpnetseminars.com/TSG/default.asp?q=157&K=CALTERA1

I hope this helps answer your question.

Regards,
Paul Hollingworth
Altera Marketing

digari@dacafe.com wrote:
> I was going through the hard copy product from altera. Methodology
> seems really promising. I just wonder where hard copy products stands
> as compare to ASIC wrt performance, power, yield & Time to market

Dig,

You really must listen to their presentation (completely).

For example, they do not recommend using S2 to prototype today for H2.

Prototyping with their FPGA means that there will be conversion issues 
that may affect the outcome.  They admit this, and wish you to succeed, 
so they want to train you how to avoid problems.  That is just good 
business.

By their own figures, somewhere between 16% and 70% of conversions will 
'suceed". (Or somewhere from 30 to 84% will FAIL).

(With EasyPath (XIlinx tm), they all succeed, and the cost is less, and 
the availability is immediate...but you are not interested in FPGAs, so 
I apologize for this digression).

With H or H2, it is just another ASIC, slightly larger, less optimal, 
but an ASIC none the less.

'Faster' is not usable, as there is no way to verify that 'faster' will 
actually work.  (In fact one high profile customer failed miserably 
because it was 'faster'!) Count on designing it for the speed you need, 
and making sure that if some delays are shorter than those in the FPGA, 
it will still work.

That said, for 2005, there are an estimated 1000 ASICs out there that 
need to be designed by the 11 vendors who do this (IBM, NEC, etc.). 
Most in 130 nm or larger (as perhaps only 3 to 5 of these will be rich 
enough to afford 90nm).  Structured ASICs are expected to capture a 
significant (you figure out what that means - 10% or 90%?  Who knows?) 
share of this market this year primarily because they allow advanced 
technologies (like 90nm) to be used.

'A' claims that are getting a design a week.  52/1000 =~ 5% of the 
designs.  That might be a lot of the $20 billion market for those 1000 
designs...

For example, LSI is advertising that their structured ASIC solution is 
more cost effective, and has a faster delivery that the A company's 
offering.

That is a real tribute to the 'A' company:  LSI considers them serious 
competition!  And, they are, as they are atempting to take LSI's bread, 
and butter from them.

That makes the 'A' company an ASIC company (as they move forward and 
start to derive revenue from this market).

Sad to see the only viable competitor leaving the field....for "greener 
grass" on the other side of the fence.

Austin

Paul Hollingworth wrote:
> Dig,
> 
> glad to hear you like the look of the methodology. Regarding your
> question, then it rather depends on whether you are talking vs
> standard-cell ASIC, or Structured ASIC. All Structured ASICs have a
> larger die size and less ultimate performance than standard-cell ASICs.
> However, they make up for this (for the majority of applications) by
> offering much lower NREs, lower minimum order quantities, reduced risk
> and better time-to-market. For the current version of HardCopy that is
> shipping today (HardCopy Stratix - based on the same 0.13um process we
> use for Stratix FPGAs), then the only really meaningful performance
> figure I can give you is that we tend to find an average of 50% speed
> up from the Stratix FPGA. We have seen typical system speeds over
> 150MHz, though with pipelining, you could achieve more. Power is lower
> than the FPGA, typically 25-40% or so. Last month we announced the next
> generation, HardCopy II, based on the same 90nm process we are using
> for the Stratix II and Cyclone II FPGAs. This will increase performance
> significantly, typically doubling what is possible on the FPGA. We
> expect "real" system performance figures of 350MHz. Power will also be
> lower and we expect core figures of 50-70% lower than the FPGA.
> 
> By yield, I assume you really mean cost. The die-size of any chip is of
> course what dominates the cost and in the case of Structured ASICs such
> as HardCopy, the die-size is larger than a fully optimised standard
> cell ASIC. However, the NRE charge will significantly lower and you
> therefore need to look at the total cost. For HardCopy Stratix, we tend
> to find above volumes of 50K-100K, standard cell ASIC tends to work out
> more cost effective, though we have seen some memorable exceptions
> where customers have gone well over these volumes, usually because
> time-to-market matters a lot more. Because HardCopy II is significantly
> more die-size optimised, (and because ASIC NREs are continuing to
> increase) we expect that the volumes at which break-even makes sense
> will increase significantly, to somewhere between 250K-500K units per
> year.
> 
> So coming to time-to-market, Structured ASICs in general are typically
> far faster to market than standard cell ASICs, because so much of the
> back-end work is already done. HardCopy is a lot faster than any other
> structured ASIC because we guarantee the migration from a working FPGA
> to the HardCopy device. The typical turnaround time to protos is 10
> weeks, including the migration in our design center and the fab and
> assembly time.
> 
> If you're interested in learning more and can spare 40 mins to an hour,
> (and can forgive a blatant plug), we did a Net Seminar on this last
> week which includes information on the latest version - HardCopy II.
> You can look at it here. (Registration required)
> http://cmpnetseminars.com/TSG/default.asp?q=157&K=CALTERA1
> 
> I hope this helps answer your question.
> 
> Regards,
> Paul Hollingworth
> Altera Marketing
> 
> digari@dacafe.com wrote:
> 
>>I was going through the hard copy product from altera. Methodology
>>seems really promising. I just wonder where hard copy products stands
>>as compare to ASIC wrt performance, power, yield & Time to market
> 
> 

digari@dacafe.com wrote:
> I was going through the hard copy product from altera. Methodology
> seems really promising. I just wonder where hard copy products stands
> as compare to ASIC wrt performance, power, yield & Time to market

Here is my, admittedly simplistic, look at the difference between X and
A.

Xilinx (EasyPath) wants to provide you with a significant cost
reduction, while eliminating any conversion issues and risks, for a
seamless transition from FPGA to EasyPath.

Altera (Hardcopy) wants to provide an ASIC that is somehow based on
your FPGA design, but does not guarantee painless (or even successful)
conversion. (If successful, the power might be lower.)

As Austin wrote, this moves Altera into the ASIC business, something
Xilinx does not want to touch with a ten-foot pole.  Been there, done
that, didn't like it at all. Just look at all the casualties...

Peter Alfke

Austin Lesea wrote:

(snip)

> Prototyping with their FPGA means that there will be conversion issues 
> that may affect the outcome.  They admit this, and wish you to succeed, 
> so they want to train you how to avoid problems.  That is just good 
> business.

(snip)

> 'Faster' is not usable, as there is no way to verify that 'faster' will 
> actually work.  (In fact one high profile customer failed miserably 
> because it was 'faster'!) Count on designing it for the speed you need, 
> and making sure that if some delays are shorter than those in the FPGA, 
> it will still work.

As far as I know, for synchronous design and zero hold time FFs,
designs should still work with faster logic.  (Not counting 
interaction with external logic that may not be synchronous.)

There is still the case of different speed grades within an FPGA
family, and tolerance within the speed grade.  I always check 
for zero hold time FF's in any new logic family that I use.

(snip)

> For example, LSI is advertising that their structured ASIC solution is 
> more cost effective, and has a faster delivery that the A company's 
> offering.

In days not so long ago there was "sea of gates", also known as 
gate array, then standard cell, and then full custom.  For sea 
of gates, more accurately as I understood it sea of transistors,
only the metal layers were custom for the design, reducing mask 
costs.   I don't know if that still exists or not.

-- glen

For me it really doesn't matter whether the solution is ASIC (hardcopy)
or FPGA (Easypath) because both are not (re)configurable.

But i see a performance and power gain in using hardcopy solution,
which is welcome in most of the cases. On the other hand   immediate
availability of easypath solution is a plus because structured
ASIC/FPGA user is always TTM hungry.

> By their own figures, somewhere between 16% and 70% of conversions
will
> 'suceed". (Or somewhere from 30 to 84% will FAIL).

this is what will increase the cost of hardcopy solution.

So a direct question:
If the volume is 30K-to -50K, who will be cheaper ??  Hardcopy or
easypath ???

An indirect question:
What is the volume range where hadrcopy is cheaper and what is the
volume range where easypath is cheaper, if I don't consider TTM and
power/performance gains.

-- Digari

Digari,

EasyPath can also be reconfigured:  IO, LUTs, DCMs, global resources are 
100% tested on every part.  So if you are clever, you could change your 
design by changing those items that are 100% tested (like the LUT).  We 
call this the ECO feature.  You may at some time in the future change 
those 100% tested items, and be guaranteed that they will function (with 
no test program changes, and no added cost to you).

Performance gains are elusive, and I do not consider that they can be 
utilized without a lot of risk.

I think that quite frankly, if either makes sense, EasyPath wins the $ 
issue for the larger devices, and H1 or H2 would win for smaller 
devices.  That is basically because EasyPath takes advantage of the fact 
that large devices have a huge amount of redundancy (tons of resources) 
that allow us to choose those parts that have fully working resources 
for the particular customer's design and save a ton of $ on test time 
testing the part for one design instead of anyone's design, whereas the 
smaller devices do not have the same statistical benefit, and test time 
is not as long either, meaning EasyPath for small parts does not allow 
us the have the same cost savings as a custom chip.

EasyPath also has a 2 for 1 special:  in order to increase volume, or 
for your own test purposes, we will check the parts for 2 working patterns.

Contact your Rep or FAE for details.

http://www.xilinx.com/products/easypath/index.htm

Austin

digari@dacafe.com wrote:
> For me it really doesn't matter whether the solution is ASIC (hardcopy)
> or FPGA (Easypath) because both are not (re)configurable.
> 
> But i see a performance and power gain in using hardcopy solution,
> which is welcome in most of the cases. On the other hand   immediate
> availability of easypath solution is a plus because structured
> ASIC/FPGA user is always TTM hungry.
> 
> 
>>By their own figures, somewhere between 16% and 70% of conversions
> 
> will
> 
>>'suceed". (Or somewhere from 30 to 84% will FAIL).
> 
> 
> this is what will increase the cost of hardcopy solution.
> 
> So a direct question:
> If the volume is 30K-to -50K, who will be cheaper ??  Hardcopy or
> easypath ???
> 
> An indirect question:
> What is the volume range where hadrcopy is cheaper and what is the
> volume range where easypath is cheaper, if I don't consider TTM and
> power/performance gains.
> 
> -- Digari
> 

"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:cvg93s$pqa2@cliff.xsj.xilinx.com...

> Sad to see the only viable competitor leaving the field....for "greener
> grass" on the other side of the fence.

There can be only ONE!!!

Regards
Falk

P.S. FPGA meet Highlander ;-)

"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:cvib32$8v41@cliff.xsj.xilinx.com...
> Digari,


> EasyPath can also be reconfigured:  IO, LUTs, DCMs, global resources are
> 100% tested on every part.  So if you are clever, you could change your
> design by changing those items that are 100% tested (like the LUT).  We
> call this the ECO feature.  You may at some time in the future change
> those 100% tested items, and be guaranteed that they will function (with
> no test program changes, and no added cost to you).

So far so good. But how is it handled by the software, especially P&R?? OK,
I could write tons of LOCs to lock out the not tested logic. But what about
routing?

Regards
Falk

Dig,

As I recall, you were asking about HardCopy versus ASIC and I attempted
to provide a reasonably balanced answer to that. The recent posts by
Xilinx in this thread are simply FUD. I have no idea where this concept
that "30-84% will fail" comes from - this is nonsense.

The whole point of HardCopy is that we guarantee that the devices will
work. Because the underlying structure of the logic is different in
HardCopy, we have a comprehensive tool flow that highlights anything
that a user should not do in the FPGA. The reason for this is that we
are optimising for die area, and so the functionality of the FPGA is a
superset of the HardCopy.

Xilinx believes that the Structured ASIC market will not amount to
anything, (and we hope they continue to believe this). Meanwhile, they
offer EasyPath, which is a way of taking defective silicon which has
failed final test and recycling it to see if the defects won't matter
in your design. I have yet to meet a customer who thinks this sounds
like a good idea. Note that this is a different approach from the
properly planned use of redundancy which deliberately builds in
additional resources up-front, which can be switched in if needed.

On the performance issue, HardCopy devices will indeed be faster.
Provided the designer has planned for this, it is of course a benefit.
The tools will tell you how much faster the HC devices will be so that
you can plan for it. This is not the same as a race hazard. EasyPath
offers no performance improvement, no power improvement and the same
need for configuration, so that you can't get rid of the config device.
(This is frequently an issue for companies planning to make their own
ASSPs).

Regarding the cost equation, there is no way that EasyPath can make
sense, simply from the die-size perspective. Here's a concrete example.
Imagine a large FPGA (from either vendor), 20mmx20mm. The gross die per
wafer on a 200mm wafer would be 56. Typical yield, calculated on the
basis of generic formulae would give a yield of 20 die per wafer. But
let's give Xilinx a LOT of credit and assume they can salvage all the
defective die on the wafer so that there are 56 die they can sell. Now
let's compare the situation with an equivalent HardCopy. I'll take a
relatively low die-size reduction figure of 66%, which gives us a die
size of 12x11mm. The gross die per wafer is now 199, and let's take a
typical net die per wafer figure assuming an average yield in 0.13um.
This gives us a NDW figure of 143.

So in the absolute BEST case for Xilinx, they get 56 die versus the 143
we get, for a wafer which costs the same to produce. That's the
production cost. To get the overall cost, you have to then factor in
the NRE and amortise that across your volume.

Hope this helps.

Paul.