Spartan-3 partial reconfiguration trouble

 Hello group.

 I am trying to get my Spartan3-based design to partially reconfigure
itself using Answer Record #18416 as a guideline
(http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?BV_UseBVCookie=yes&getPagePath=18416).
My design basically implements a custom MCU with code/data in BRAM, and
an audio processing structure --which is actually the section I am
interested in reconfiguring dynamically-- consisting of a bunch of
filters that use SP-3 embedded multipliers, some accumulators and
distributed RAM. I also prepared my design for partial reconfiguration
following the information available in Application Note #290
(http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf).

 To carry out the reconfiguration process, my board exports some FPGA
IOs to the external configuration interface and then these are
controlled by the custom embedded MCU running inside the same FPGA
(http://www.nongnu.org/s430/). The difference bitstream is read by the
MCU from an external memory card. However when it attempts to perform
the reconfiguration weird things happen. Most of the time the boards
just freezes and sometimes the chip turns really hot (which reminds me
that I am literally playing with fire here :P ).

 I have never been able to successfully reconfigure the device using
this method. Perhaps, as the answer record points out, this has
something to do with the unmodified bits resetting during
reconfiguration. Are there any other procedures or gotchas I am not
aware of? The method to break down the design for partial
re-configuration is really cumbersome and I may be doing several
mistakes there. Is there a way to instruct ISE to break the design
automatically?

 Also, does somebody know if there is an update on the status of the
hidden ICAP of the SP-3? Is this actually usable? I recall reading in a
previous post some months ago that someone at Xilinx (Austin Lesea?)
was going to find out if there was a way to make it work.

 The whole idea of my project is to use partial-reconfiguration to
support many types of audio filters (this is an audio effects
processor). Maybe it is going to be much better to ditch my current
SP-3 design in favor of a Virtex one that supports modular blocks. Am I
right?

 Best regards.

--
PabloBleyerKocik /
pbleyer         /"Reliable software must kill people reliably."
@embedded.cl   / -- Andy Mickel

"Pablo Bleyer Kocik" <pablobleyer@hotmail.com> schrieb im Newsbeitrag
news:1109170182.442577.56910@o13g2000cwo.googlegroups.com...
> Hello group.
>
>  I am trying to get my Spartan3-based design to partially reconfigure
> itself using Answer Record #18416 as a guideline
>
(http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?BV_UseBVCookie=yes&get
PagePath=18416).

[snip]
>  The whole idea of my project is to use partial-reconfiguration to
> support many types of audio filters (this is an audio effects
> processor). Maybe it is going to be much better to ditch my current
> SP-3 design in favor of a Virtex one that supports modular blocks. Am I
> right?
>
>  Best regards.

Hi
first many congratulations for th s430, I assume it yours ?

yes I am afraid you are about right - the S3 partial reconfig -
my guess is nobody is using it, it could be useable but the
effort to get it done could be too high to be reasonable.

it could, OTOH maybe you just about to get it working
the way you are trying. But dont expect much help,
its nomans land where you are walking!
ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig.
(maybe thats outdated info, but I had/have that impression)

Antti

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:cvigln$1tl$02$1@news.t-online.com...
> "Pablo Bleyer Kocik" <pablobleyer@hotmail.com> schrieb im Newsbeitrag
> news:1109170182.442577.56910@o13g2000cwo.googlegroups.com...
> > Hello group.
> >
> >  I am trying to get my Spartan3-based design to partially reconfigure
> > itself using Answer Record #18416 as a guideline
> >
>
(http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?BV_UseBVCookie=yes&get
> PagePath=18416).
>
> [snip]
> >  The whole idea of my project is to use partial-reconfiguration to
> > support many types of audio filters (this is an audio effects
> > processor). Maybe it is going to be much better to ditch my current
> > SP-3 design in favor of a Virtex one that supports modular blocks. Am I
> > right?
> >
> >  Best regards.
>
> Hi
> first many congratulations for th s430, I assume it yours ?
>
> yes I am afraid you are about right - the S3 partial reconfig -
> my guess is nobody is using it, it could be useable but the
> effort to get it done could be too high to be reasonable.
>
> it could, OTOH maybe you just about to get it working
> the way you are trying. But dont expect much help,
> its nomans land where you are walking!
> ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig.
UUPS, typo:
I meant "Xilinx has NO interest in S3 partial reconfig..."

> (maybe thats outdated info, but I had/have that impression)
>
> Antti
>
>

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:cvigln$1tl$02$1@news.t-online.com...

> >  The whole idea of my project is to use partial-reconfiguration to
> > support many types of audio filters (this is an audio effects
> > processor). Maybe it is going to be much better to ditch my current
> > SP-3 design in favor of a Virtex one that supports modular blocks. Am I
> > right?

There are many ways to skin a cat. Different filters can also be realized by
keeping the processing structure (MACs, delays etc.) but just reloading
filter coefficients, which can be done using BRAM, SRL16, SelectRAM.
Or go for a complete hazzle free approach, reconfigure the whole FPGA and
keep an (complete) FPGA image for every different filter in FLASH memory
(its cheap)

Regards
Falk

 Hello Antti. Thanks for your reply.

Antti Lukats wrote:
> Hi
> first many congratulations for th s430, I assume it yours ?

 Yes, the beast is mine. It was just a small hobby project I started
working on many months ago to fight boredom and it was victim of the
snowball effect. I am afraid I have actually grown very dependent of my
own creation. ;) Although the MSP430 is not an ideal architecture for
FPGAs, the core size and code density is very good, and I am able to
use the GCC toolchain seamlessly with it. Really, I have been able to
do wonderful things with just 2 BlockRAMs. And when I ported it to
Spartan-3 I got a multiplier peripheral almost for free, so the
floating point routines now run very happily ever after. :)

 I have now a pipelined version that allows faster clocking. Sadly I
don't have very much spare time left in order to verify and write-back
the changes to the CVS faster.

> yes I am afraid you are about right - the S3 partial reconfig -
> my guess is nobody is using it, it could be useable but the
> effort to get it done could be too high to be reasonable.
>
> it could, OTOH maybe you just about to get it working
> the way you are trying. But dont expect much help,
> its nomans land where you are walking!
> ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig.
> (maybe thats outdated info, but I had/have that impression)

 Hmmm... I am very sorry to realize this. It would be nice to hear from
someone who has actually used the reconfiguration capabilities of the
device. Maybe it is *not* reconfigurable at all and I am just wasting
my time! :S

 I will keep trying, as you say. But I am afraid that, if I eventually
get this to work, I will have to battle with the design every time I
change the filter parameters or generate a new filter. The front effort
was going to be worth only if the filter management was streamline
after that...

  Thanks again. Best regards.

--                /"If you would not be forgotten
PabloBleyerKocik / As soon as you are dead and rotten,
pbleyer         / Either write things worth reading,
@embedded.cl   / Or do things worth writing."- Benjamin Franklin

 Hello Falk. Thanks for answering.

Falk Brunner wrote:
> There are many ways to skin a cat. Different filters can also be
realized by
> keeping the processing structure (MACs, delays etc.) but just
reloading
> filter coefficients, which can be done using BRAM, SRL16, SelectRAM.

 I am already doing this for some kind of filters when it is possible
to do so. For example, my delays always have maximum taps and I control
bypass writing to a memory-mapped register with the MCU. Then I get
only the taps I need. The problem is that there are many audio
processing structures that are very, very different. I even have a
morph engine that stores an evolvent in *big* distributed RAM (takes
almost all of the available slices of the FPGA), in order to convolve
it with an incoming signal. The only way I can do this is to re-use
most of the FPGA area available.

> Or go for a complete hazzle free approach, reconfigure the whole FPGA
and
> keep an (complete) FPGA image for every different filter in FLASH
memory
> (its cheap)

 That was my first approach, but then I will need an external
controller which is what I am trying to avoid, since I already need and
have the MCU inside...

 Thank you for your suggestions. Regards.

--
PabloBleyerKocik /"Artificial Intelligence: the art of making
pbleyer         / computers that behave like the ones in movies."
@embedded.cl   / -- Bill Bulko

Pablo Bleyer Kocik wrote:
>  Hello Antti. Thanks for your reply.
> 
> Antti Lukats wrote:
> 
>>Hi
>>first many congratulations for th s430, I assume it yours ?
> 
> 
>  Yes, the beast is mine. It was just a small hobby project I started
> working on many months ago to fight boredom and it was victim of the
> snowball effect. I am afraid I have actually grown very dependent of my
> own creation. ;) Although the MSP430 is not an ideal architecture for
> FPGAs, the core size and code density is very good, and I am able to
> use the GCC toolchain seamlessly with it. Really, I have been able to
> do wonderful things with just 2 BlockRAMs. And when I ported it to
> Spartan-3 I got a multiplier peripheral almost for free, so the
> floating point routines now run very happily ever after. :)
> 
>  I have now a pipelined version that allows faster clocking. Sadly I
> don't have very much spare time left in order to verify and write-back
> the changes to the CVS faster.
> 
> 
>>yes I am afraid you are about right - the S3 partial reconfig -
>>my guess is nobody is using it, it could be useable but the
>>effort to get it done could be too high to be reasonable.
>>
>>it could, OTOH maybe you just about to get it working
>>the way you are trying. But dont expect much help,
>>its nomans land where you are walking!
>>ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig.
>>(maybe thats outdated info, but I had/have that impression)
> 
> 
>  Hmmm... I am very sorry to realize this. It would be nice to hear from
> someone who has actually used the reconfiguration capabilities of the
> device. Maybe it is *not* reconfigurable at all and I am just wasting
> my time! :S
> 
>  I will keep trying, as you say. But I am afraid that, if I eventually
> get this to work, I will have to battle with the design every time I
> change the filter parameters or generate a new filter. The front effort
> was going to be worth only if the filter management was streamline
> after that...
> 
>   Thanks again. Best regards.

I have had email exchanges with a person at Xilinx about this.  None of 
the Spartan chips are currently supported, but I have been told that 
Xilinx is "committed" to providing partial-reconfiguration for the 
Spartan 3 chips (this was over a year ago, so I'm not sure what 
"committed" really means ;).  There are two problems with getting PR 
working in the Spartan 3.

The first issue is the fact that PR has used tristate buffers to connect 
to long lines to provide the intermodule connections.  This has worked 
in the Virtex family.  However the V4 chips also have no tristate 
buffers.  So Xilinx is working on that problem and I expect their 
solution will be portable to the S3 parts.

But the second problem is the lack of interest in S3 PR in the customer 
base.  I am surprised at this since it can make the difference between a 
$10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash memory.

I believe you are looking to use PR the same way I want to.  You don't 
need to do it on the fly with the rest of the chip running, you just 
need to download modules in different combinations to provide the final 
download that suits the current need.  But I may be mistaken here.  If 
you don't have an external processor to load the FPGA, were you planning 
to use the internal proc to do that?  I may be mistaken, but I think 
there is a special block in the FPGA to allow internal logic to load a 
new design (I forget the name, it may be IMAP).  I seem to recall that 
the Spartan 3 does not have this block so PR must be controlled from the 
outside.

There are some limitations to loading the partial configuration while 
the rest of the chip is alive.  It may be that you just plain can't do 
it, or it may just be that the chip does not allow blocks adjacent to 
the partial load to be active.  There are also limitations in that an S3 
PR block must use full columns while the Virtex chips (or maybe just V4) 
can load partial columns.  I do recall that the S3 is much more limited 
in the way it can do PR than the Virtex parts.



Rick Collins

rick.collins@XYarius.com

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design       http://www.arius.com
4 King Ave.                               301-682-7772 Voice
Frederick, MD 21701-3110     GNU tools for the ARM http://www.gnuarm.com

 Hello Rick.

rickman wrote:
> I have had email exchanges with a person at Xilinx about this.  None
of
> the Spartan chips are currently supported, but I have been told that
> Xilinx is "committed" to providing partial-reconfiguration for the
> Spartan 3 chips (this was over a year ago, so I'm not sure what
> "committed" really means ;).  There are two problems with getting PR
> working in the Spartan 3.

 Yes, I read your previous posts on the subject.

> The first issue is the fact that PR has used tristate buffers to
connect
> to long lines to provide the intermodule connections.  This has
worked
> in the Virtex family.  However the V4 chips also have no tristate
> buffers.  So Xilinx is working on that problem and I expect their
> solution will be portable to the S3 parts.

 Wow, that is something new. I didn't know they had dropped the TBUFs
in Virtex-4! Does this mean that Virtex-4 is not reconfigurable by
modules?

> But the second problem is the lack of interest in S3 PR in the
customer
> base.  I am surprised at this since it can make the difference
between a
> $10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash
memory.

 Exactly. A single chip solution is worthwhile on its own sake.

> I believe you are looking to use PR the same way I want to.  You
don't
> need to do it on the fly with the rest of the chip running, you just
> need to download modules in different combinations to provide the
final
> download that suits the current need.  But I may be mistaken here.
If
> you don't have an external processor to load the FPGA, were you
planning
> to use the internal proc to do that?

 I have a known-good initial bitstream in a configuration Flash (the
'boot' image). After that I disable it and I read data from a memory
card, including the other bitstreams.

> I may be mistaken, but I think
> there is a special block in the FPGA to allow internal logic to load
a
> new design (I forget the name, it may be IMAP).  I seem to recall
that
> the Spartan 3 does not have this block so PR must be controlled from
the
> outside.

 That is the ICAP block I was asking about. It seems the SP-3 has an
ICAP but it either doesn't work or there are no tools to use it.

> There are some limitations to loading the partial configuration while

> the rest of the chip is alive.  It may be that you just plain can't
do
> it, or it may just be that the chip does not allow blocks adjacent to

> the partial load to be active.  There are also limitations in that an
S3
> PR block must use full columns while the Virtex chips (or maybe just
V4)
> can load partial columns.  I do recall that the S3 is much more
limited
> in the way it can do PR than the Virtex parts.

 Yes. I am assuming appnote 290 applies to Spartan-3 also, I used it to
prepare my design for PR. Many Xilinx documentation refer to SP-3s
partially reconfiguring, but I haven't found the definitive reference
yet...

 Cheers.

PabloBleyerKocik /"Person who say it cannot be done
pbleyer         / should not interrupt person doing it."
@embedded.cl   / -- Chinese proverb

Pablo Bleyer Kocik wrote:
>  Hello Rick.
> 
> rickman wrote:
> 
>>I have had email exchanges with a person at Xilinx about this.  None of
>>the Spartan chips are currently supported, but I have been told that
>>Xilinx is "committed" to providing partial-reconfiguration for the
>>Spartan 3 chips (this was over a year ago, so I'm not sure what
>>"committed" really means ;).  There are two problems with getting PR
>>working in the Spartan 3.
> 
> 
>  Yes, I read your previous posts on the subject.
> 
> 
>>The first issue is the fact that PR has used tristate buffers to connect
>>to long lines to provide the intermodule connections.  This has  worked
>>in the Virtex family.  However the V4 chips also have no tristate
>>buffers.  So Xilinx is working on that problem and I expect their
>>solution will be portable to the S3 parts.
> 
> 
>  Wow, that is something new. I didn't know they had dropped the TBUFs
> in Virtex-4! Does this mean that Virtex-4 is not reconfigurable by
> modules?

V4 still has full PR capability, but the old software does not support 
it.  I have been told they are actively working on the software to 
support PR in the V4 chips.  In fact, V4 has more capability I believe 
in that it can be configured in partial columns.


>>But the second problem is the lack of interest in S3 PR in the customer
>>base.  I am surprised at this since it can make the difference between a
>>$10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash memory.
> 
>  Exactly. A single chip solution is worthwhile on its own sake.
> 
> 
>>I believe you are looking to use PR the same way I want to.  You don't
>>need to do it on the fly with the rest of the chip running, you just
>>need to download modules in different combinations to provide the final
>>download that suits the current need.  But I may be mistaken here. If
>>you don't have an external processor to load the FPGA, were you planning
>>to use the internal proc to do that?
> 
> 
>  I have a known-good initial bitstream in a configuration Flash (the
> 'boot' image). After that I disable it and I read data from a memory
> card, including the other bitstreams.

Do you require the FPGA to be running when you load the other bitstreams.

>>I may be mistaken, but I think
>>there is a special block in the FPGA to allow internal logic to load a
>>new design (I forget the name, it may be IMAP).  I seem to recall that
>>the Spartan 3 does not have this block so PR must be controlled from the
>>outside.
> 
> 
>  That is the ICAP block I was asking about. It seems the SP-3 has an
> ICAP but it either doesn't work or there are no tools to use it.

If it is there, I am pretty sure it does not support configuration.

>>There are some limitations to loading the partial configuration while
>>the rest of the chip is alive.  It may be that you just plain can't do
>>it, or it may just be that the chip does not allow blocks adjacent to
> 
> 
>>the partial load to be active.  There are also limitations in that an S3
>>PR block must use full columns while the Virtex chips (or maybe just V4)
>>can load partial columns.  I do recall that the S3 is much more limited
>>in the way it can do PR than the Virtex parts.
> 
> 
>  Yes. I am assuming appnote 290 applies to Spartan-3 also, I used it to
> prepare my design for PR. Many Xilinx documentation refer to SP-3s
> partially reconfiguring, but I haven't found the definitive reference
> yet...

APP290 does not apply to S3 yet.  What docs talk about PR in S3s?

rickman wrote:
> >  I have a known-good initial bitstream in a configuration Flash
(the
> > 'boot' image). After that I disable it and I read data from a
memory
> > card, including the other bitstreams.
>
> Do you require the FPGA to be running when you load the other
bitstreams.

 It is the only way I will be able to load bitstreams from the memory
card and do a couple of other things at the same time.

> APP290 does not apply to S3 yet.  What docs talk about PR in S3s?

 At least the datasheet mentions it (regarding the SelectMAP
interface). Also XAPP462 refers to it in the bitgen generation section.
An there is the #18416 Answer Record...

 Cheers.

--
PabloBleyerKocik /"But what... is it good for?"
 pbleyer        / -- 1968 Engineer at IBM's Advanced Computing
  @embedded.cl / Systems Division, commenting on the microchip