Prescalable counter

Hi everyone..

I wonder how to build a prescaled counter! That is a counter that can be 
prescaled by fx. a factor 1.000.000 or less!

Any nice ideas how to do this?


Thanks
Preben

Hi,

When using Xilinx, the SRL16 is a very good candidate for prescaler implementation.

G�ran

Preben Holm wrote:
> Hi everyone..
> 
> I wonder how to build a prescaled counter! That is a counter that can be 
> prescaled by fx. a factor 1.000.000 or less!
> 
> Any nice ideas how to do this?
> 
> 
> Thanks
> Preben

Prescalers are mostly used to increase the max frequency resolution.
What is it you are after?
Peter Alfke

what is this counter for?


"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message
news:421deb0f$0$29285$14726298@news.sunsite.dk...
> Hi everyone..
>
> I wonder how to build a prescaled counter! That is a counter that can be
> prescaled by fx. a factor 1.000.000 or less!
>
> Any nice ideas how to do this?
>
>
> Thanks
> Preben

Vladislav Muravin wrote:
> what is this counter for?


It is supposed to be a candidate for doing sampling on signals and 
therefore addressing memory at a "high" speed!


Thanks

G�ran Bilski wrote:
> Hi,
> 
> When using Xilinx, the SRL16 is a very good candidate for prescaler 
> implementation.
> 

In which way would you use this shift register LUT for prescaler 
implementation!

Preben,
it's a deal: You tell us no details, we give you no advice. That's what
you seem to want.
Peter Alfke

> it's a deal: You tell us no details, we give you no advice. That's what
> you seem to want.

I would like to give you guys details... I just don't have the 
"home-cooked" code on this computer!

And I don't think I can say a lot more (not because I don't will, but 
because my english stinks and because I can't explain it any better).

I need to address memory at different speeds. Therefore I need to be 
able to prescale.
I need to address the memory at the same intervals to be able to save 
data. The data comes from an analog-to-digital converter that should 
sample different data's with regular intervals (namely at the same speed 
of the counter).

The whole idea is to build the sampling part of an digital oscilloscope. 
This should include sampling, triggering as in an digital storage 
oscilloscope.

For any further details please ask again! Maybe I forget that I haven't 
told you what I'm trying to build in details, but I myself don't even 
know all the details (as I just started the project)!


Thanks for helping!

Preben, your English is ok, better than my limited Danish.
You want to build a sampling scope (so do I).
You must start with the A/D vonverter, for that's where most of you
money goes.
That determines the sampling rate = clock, and you must have low
jitter!
The rest is not too complicated. You can use on-chip BlockRAM, but you
need an interface to external DRAM ( cheap and easily available). I
suppose you move all the display and human interface problems onto the
PC (that's what I would do). Saves you a lot of work and assures good
looks.
Now, designig a counter should be the least of your problems...
Or, to put it differently: If you have problems with a counter, this
project is too big for you. Do something simpler.
Good luck.
Hilsen
Peter Alfke

Preben Holm wrote:
> 
> The whole idea is to build the sampling part of an digital oscilloscope. 
> This should include sampling, triggering as in an digital storage 
> oscilloscope.

  For that, you need 1:2:5:10:20:50:100 for the best human friendly 
timebase (rather than a long binary counter).

  You can code as above, with taps, and a single MUX, or you could have
a first stage that can select a choice of divide by /1/2/5/10, as a 
clock enable into following cascaded /10 stages that select 
10/100/1000/10000 etc.

  If you were being 'register frugal', (eg using a CPLD),
then the first stage of
/1/2/5/10/20/50 is 6 bits wide, and follow that with a number
of /100 cascades [7 bits]

  The output of this divider chain would be conditioned to be one clock 
wide, and feed as ClkEnable into the simple binary-memory 
scanning/loading counter - the scanner counter needs a trigger state 
engine to Start on Signal trigger, and stop at MAX (or sooner if set).

-jg