FPGA interface to an asynchronous microcontroller memory bus

Hi everybody,

I have to interface a 8-bit microcontroller (ATMega128, running at 16MHz) to
a Xilinx Spartan-II FPGA.

The FPGA will have several roles. It should be an address latch (the bus has
address/data multiplexed), an address decoder (to generate chip selects)
and a peripheral accessible through memory-mapped registers.

As the bus is asynchronous, I suppose I'll have to over-sample the signals.
Could anyone direct me to some documentation about asynchronous bus
interfaces for FPGAs ? The FPGA main clock runs at 24MHz, and I'd like to
know if this will be enough (the clock can be doubled using a DLL if
needed).

Thanks in advance for your help.

Laurent Pinchart

The computer must give you some strobe that indicates valid data.
Do a worst-case analysis whether your FPGA clock guarantees capture
within that window.
Otherwise implement dirct data capture in the IOB and postpone the
synchronization to 24 MHz.
Always assume worst-case timing and phasing...
Peter Alfke

"Laurent Pinchart" <laurent.pinchart@skynet.be> wrote
> The FPGA main clock runs at 24MHz, and I'd like to
> know if this will be enough (the clock can be doubled using a DLL if
> needed).
Laurent,
No, you can't.
From DS001
FCLKINLF Input clock frequency (CLKDLL) Min(-6) 25 Max(-6) 100 Min(-5) 25
Max(-5) 90 MHz
Cheers, Syms.

Symon wrote:

>> The FPGA main clock runs at 24MHz, and I'd like to
>> know if this will be enough (the clock can be doubled using a DLL if
>> needed).

> No, you can't.
> From DS001
> FCLKINLF Input clock frequency (CLKDLL) Min(-6) 25 Max(-6) 100 Min(-5) 25
> Max(-5) 90 MHz

Oops, you're right. I'll then use a 25MHz main clock, or keep the current
one if 24MHz turns out to be enough. My initial question still applies
though :-)

Laurent Pinchart

> The computer must give you some strobe that indicates valid data.
> Do a worst-case analysis whether your FPGA clock guarantees capture
> within that window.
> Otherwise implement dirct data capture in the IOB and postpone the
> synchronization to 24 MHz.
> Always assume worst-case timing and phasing...

The microcontroller has read, write and address strobe signals. The problem
is that the bus is asynchronous, which means that the FPGA might sample the
signals when they are not in a defined logic state. This implies
meta-stability problems if I remember my classes properly. What are the
basic guidelines to handle such problems ?

Laurent Pinchart

"Laurent Pinchart" <laurent.pinchart@skynet.be> wrote in message
news:4223a767$0$30170$ba620e4c@news.skynet.be...
>
> The FPGA will have several roles. It should be an address latch (the bus
has
> address/data multiplexed), an address decoder (to generate chip selects)
> and a peripheral accessible through memory-mapped registers.
>

I don't know what peripheral  you want to implement, but for  an address
latch / decoder an FPGA sounds like an overkill.
Spartan-II is not expensive, but consider the power supply and sereal EEPROM
etc.
A CPLD may be a simplier solution. Say 9572?

On Tue, 01 Mar 2005 01:58:18 +0100, Laurent Pinchart
<laurent.pinchart@skynet.be> wrote:

>> The computer must give you some strobe that indicates valid data.
>> Do a worst-case analysis whether your FPGA clock guarantees capture
>> within that window.
>> Otherwise implement dirct data capture in the IOB and postpone the
>> synchronization to 24 MHz.
>> Always assume worst-case timing and phasing...
>
>The microcontroller has read, write and address strobe signals. The problem
>is that the bus is asynchronous, which means that the FPGA might sample the
>signals when they are not in a defined logic state. This implies
>meta-stability problems if I remember my classes properly. What are the
>basic guidelines to handle such problems ?

The FPGA will do many things in parallel. One of the things it will do
is a latch that's clocked by the appropriate edge from the AVR that is
independent of any logic that's changed by the FPGA's clock. After the
data is latched, it will set a "new data available" flag that's handled
by the FPGA's clocked logic. 

-- 
Rich Webb   Norfolk, VA

No problem. In Frequency Synthesis mode (Fx output), it is only the
output frequency (not the input frequency) that must be above 24 MHz...
Peter Alfke

There was a descent thread of a PC104 (ISA) bus a while back.  Try
googling "Async logic in FPGAs"

BTW, sometimes MPU's give bus timing with respect to the chip's clock
input.

- Newman

Peter,
Spartan II doesn't have frequency synthesis mode or an FX output. This makes
it difficult to use in the mode you suggest.
Cheers, Syms.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:1109641138.681743.237750@z14g2000cwz.googlegroups.com...
> No problem. In Frequency Synthesis mode (Fx output), it is only the
> output frequency (not the input frequency) that must be above 24 MHz...
> Peter Alfke
>