FPGA interface to an asynchronous microcontroller memory bus

> We handle this situation in this way.
> NO oversampling. Since there is no need to do so.
> A read acces to a register inside the FPGA is plain combinatorical, no
> problem here.
> A write access to a register is defacto a clocked process, so we use WR as
> a clock (on a global clock net) to load data into FPGA registers.

> For an address latch its similar, use ALE to clock the address into the
> latch/register. Here you dont need to wast a global clock net, local
> routing (low skew lines) do fine, since the latch is small (just a
> handfull of flipflops)

Ok, that's nice, will save a global clock net.

>> The FPGA will do many things in parallel. One of the things it will do
>> is a latch that's clocked by the appropriate edge from the AVR that is
>> independent of any logic that's changed by the FPGA's clock. After the
>> data is latched, it will set a "new data available" flag that's handled
>> by the FPGA's clocked logic.
> 
> The right way to go. Dont forget to synchronize the flag using the classic
> 1/2 flipflop synchronizer.

Forgive my ignorance, but where can I find documentation about that ? Is at
a half flipflop or a 1-or-2 fliflop ? :-)

I also would appreciate pointers to some good FPGA design tutorial. I can
find VHDL tutorials all over the net, but they only cover the basics, not
the design methodology. I haven't been able to find a good book about it.

Laurent Pinchart