Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...

Those are the subjets of the next webseminar. Over 700 engineers have
signed up already.
You can still join us this Tuesday (11:00 Pacific Time) when Dr. Howard

Johnson explains the effects of ground bounce and crosstalk caused
by simultaneously switching outputs. This is a highly technical talk
(you will love it) with many screen shots taken with an 8 GHz scope,
and with detailed comparisons of good and bad BGA packages.

I give the short introduction and conclusion, but it is Howard's show.
You may know him as the author of "High-speed Digital Design", the
standard reference book found on many of our bookshelves (and benches).

Howard is not only a well-known and respected expert in this
treacherous field, he is also a lively speaker and an excellent
teacher. Enjoy !
You can register for this live webseminar, and also for the
two archived predecessors:

http://www.xilinx.com/events/webcasts/tol/01feb05.htm

Peter Alfke, Xilinx Applications

I think Howard Johnson gave a super presentation, definitely
"technical". We had 800 listeners, and we got lots of questions. From
my point of view, it was a smashing success. The newsgroup is still
very quiet, maybe that is better than the biting and bitching after the
prior seminars ...
Coincidentally (?) Altera had a press release about Signal Integrity on
the same day. Their David Greenfield (of comp.arch.fpga fame...) claims
that "benchmarks demonstrate another significant advantage...", but
their press release tells us that Altera's benchmark claims come from
simulations based on IBIS models.

On our board, we measured and compared the real hardware, for both
families, under identical condition. I prefer an 8 GHz Tektronix scope
picture over an IBIS-based simulation any time of the day. More work,
more expensive, but definitely more believable and more encompassing.
Peter Alfke, from home.

Still no comments on the newsgroup.
Those of you who want to (re)visit Howard Johnson's presentation can do
this by clicking on

http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf

Peter Alfke, Xilinx Applications

Peter,

I suppose they are still digesting Howards presentation....

Bottom line, the new SparseChevron(tm) package for V4 has substantial 
benefits which enable the high speed designs to work.

It doesn't help to have better dI/dt if all it does is create SI 
problems.  Perhaps we design our IOs to meet requirements, such that 
they can actually be used? (Answer: yes we do.  It is part of the 
requirements not to 'blow the lid off' with dI/dt that would be of no 
benefit to a customer).

The key is what is going to happen when all the IOs (and CLBs) in your 
application do what you want them to do:  will the noise trash the IO? 
will the noise cause so much jitter during the "boing" (I love HJ's 
sound effects...) that the timing margins are violated, and errors result?

Errors caused by system jitter (which in turn is caused by ground & 
supply bounce, which in turn is caused by SSOs and logic toggling) is 
the number one SI problem in high speed designs today (and not exclusive 
to FPGAs at all).

Austin

Peter Alfke wrote:
> Still no comments on the newsgroup.
> Those of you who want to (re)visit Howard Johnson's presentation can do
> this by clicking on
> 
> http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
> 
> Peter Alfke, Xilinx Applications
> 

"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag
news:1109786492.673401.81320@f14g2000cwb.googlegroups.com...

> Still no comments on the newsgroup.

Nevously waiting??

> Those of you who want to (re)visit Howard Johnson's presentation can do
> this by clicking on
>
> http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf

Another strike against Altera. Hmm, the differences are clearly visible,
explinations sound reasonable. If we assume that PR had not too much
possibilities to fake, aeehhh, arrange the data, this looks like a clear
victory for Xilinx, does it?

Regards
Falk

It was a good presentation, got to learn a couple of new thing, and
have new ideas. Right now, I have a question though, about packaging
and interconnection. I was just looking at the old AFX prototype board
for the venerable XCV series of FPGA, and then I ask myself that
question of how does those P4 chip actually resolve their SI issues,
without using BGA and being placed on sockets! considering they draw
~50W (i might be wrong here, but its a lot of current...); wouldnt this
introduce parasitic inductance, hence ground loops and eventually noise
induce in "victims" pins?

thanks
Jacques

Hi!

I really enjoyed the presentation. I didn't realize how fast the time passed
and before I was able to write down all my questions it was all over. So
next time reserve at least 1/2 hour for QA session. Besides the comparison
between Virtex-4 and Stratix-2 I was hoping to see comparison between
Virtex-II/Pro and Virtex-4.

Regards,
Igor Bizjak

"Peter Alfke" <peter@xilinx.com> wrote in message
news:1109786492.673401.81320@f14g2000cwb.googlegroups.com...
> Still no comments on the newsgroup.
> Those of you who want to (re)visit Howard Johnson's presentation can do
> this by clicking on
>
> http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
>
> Peter Alfke, Xilinx Applications
>

There was no hanky-panky.
We designed the dual-board to be as good as possible, and strictly
identical (or fair) on both halves.
And Howard did his analysis with no pre-conceived answers.
Marketing was completely out of the loop (doesn't always work that way)
and Howard Johnson has obviously too much invested in his own
reputation to even think of risking that on any shady deals...
This was pure science, and a fun project.
That the results are heavily in our favor is a just reward for having
designed things the proper way.
Peter Alfke

Jacques,

A socket makes things worse, but only by the dimension of the distance 
as a ratio to the total distance.

So, for HJ, he assumed a 0.035" trip into the pcb, and a smaller number 
for the package (because packages are thinner).

Add another ? inches (or cm, mm, or whatever) and that makes the 
vertical loop larger, and will increase the noise in the proportion of 
the added distance. Yes, a socket makes it worse.

That is why there are (very expensive) low profile sockets (to reduce 
the inductance of the socket path).

Sockets just make everybody worse.  If the toal loop is small to start 
with, then doubling it doubles the noise.

If the loop was terrible to start with, adding the same distance to it 
as before hardly makes anything worse.

One thing is true:  once you start with a good package, you can make it 
worse (with a socket, or bad pcb layout).

It is also ture that once you start with a marginal or poor package, 
there is nothing at all you can do to make it better (and hardly 
anything makes it worse because it is so bad already).

A comment that was made, but HJ couldn't get to answer was: "If you use 
virtual grounds (IOs as ground), won't that improve the noise (make it 
smaller)."  The answer is yes, it will.  But, using IOs as grounds is 
not as effective as a real ground, and any part that uses IOs as grounds 
improves (does not uniquely apply to a bad package only).

Prior to the V4 packages, we had made as many improvements as we could 
have made at that time, knowing what we knew.  Those V2, V2P packages 
don't fare (all that) poorly in comparison to the new SparseChevron 
packages (worse by ~2:1 in terms of inductance of loops), but are still 
better than other 'competitive' FPGA packages.  As HJ said, it is all in 
the number of power and ground pins, their arrangement, and the 
bypassing on chip (to make power and ground pins equivalent from a 
signal return point of view).

Austin

jaxato@gmail.com wrote:
> It was a good presentation, got to learn a couple of new thing, and
> have new ideas. Right now, I have a question though, about packaging
> and interconnection. I was just looking at the old AFX prototype board
> for the venerable XCV series of FPGA, and then I ask myself that
> question of how does those P4 chip actually resolve their SI issues,
> without using BGA and being placed on sockets! considering they draw
> ~50W (i might be wrong here, but its a lot of current...); wouldnt this
> introduce parasitic inductance, hence ground loops and eventually noise
> induce in "victims" pins?
> 
> thanks
> Jacques
> 

Igor,

We did that too.  As I already posted, the difference was about 2:1 
better with the new V4 packages.

Even our previous packages were not all that bad.  But, they could be 
improved upon, so we did for this generation.

For a first order comparison, look at the di/dt for V2P (about the same 
as V4), and the ball pattern.  Count the average IO per power/ground pin 
ratio and examine placement to compare the two.

Ultimately, we have the SSO table to reflect the package capabilities, 
so if you are within those guidelines, there is no performance penalty 
expected.  We also consider other factors in the tables (like system 
jitter, not just Vil(max)), so designers have succesful boards, and we 
do not get cases.

Austin

IgI wrote:

> Hi!
> 
> I really enjoyed the presentation. I didn't realize how fast the time passed
> and before I was able to write down all my questions it was all over. So
> next time reserve at least 1/2 hour for QA session. Besides the comparison
> between Virtex-4 and Stratix-2 I was hoping to see comparison between
> Virtex-II/Pro and Virtex-4.
> 
> Regards,
> Igor Bizjak
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:1109786492.673401.81320@f14g2000cwb.googlegroups.com...
> 
>>Still no comments on the newsgroup.
>>Those of you who want to (re)visit Howard Johnson's presentation can do
>>this by clicking on
>>
>>http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
>>
>>Peter Alfke, Xilinx Applications
>>
> 
> 
>