SR latches in Xilinx devices?

What's the party line on using SR's on Xilinx FPGAs (ie. two
cross-coupled NAND gates, or some equivalent representation?) Can the
timing analyser cope?

The dev guide has a few hits on the words 'asynchronous' and
'feedback', but none of them are relevant.

Thanks -

Rick

Richard Thompson wrote:
> What's the party line on using SR's on Xilinx FPGAs (ie. two
> cross-coupled NAND gates, or some equivalent representation?) Can the
> timing analyser cope?
>
> The dev guide has a few hits on the words 'asynchronous' and
> 'feedback', but none of them are relevant.
>
> Thanks -
>
> Rick

Generally speaking you're asking for trouble when you try to
make asynchronous sequential circuits using LUTs.  You just
can't force the tools to make the coverage terms for state
transition.  In most Xilinx parts you can use actual flip-flops
to get SR's (see FDCP in the libraries guide).

On 1 Mar 2005 06:16:36 -0800, "Gabor" <gabor@alacron.com> wrote:

>Generally speaking you're asking for trouble when you try to
>make asynchronous sequential circuits using LUTs.  You just
>can't force the tools to make the coverage terms for state
>transition.  In most Xilinx parts you can use actual flip-flops
>to get SR's (see FDCP in the libraries guide).

Luckily, not an issue here - the standard cross-coupled NAND is
already hazard-free (unless the mapper decides to reimplement it,
which seems unlikely).

My main concern is trce - do you know if the timing analyser will
trace through the the S/R ports on an FDCP? I can't see anything
obvious in the documentation. Presumably it won't be able to handle
explicit cross-coupled gates, though.

Rick

Richard Thompson wrote:

> Luckily, not an issue here - the standard cross-coupled NAND is
> already hazard-free (unless the mapper decides to reimplement it,
> which seems unlikely).

Hazard-free as long as the set and reset pulses
are well formed and far enough apart in time.
It's not difficult to make an oscillation
burst otherwise.

           -- Mike Treseler

On Tue, 01 Mar 2005 10:09:52 -0800, Mike Treseler
<mike_treseler@comcast.net> wrote:

>Richard Thompson wrote:
>
>> Luckily, not an issue here - the standard cross-coupled NAND is
>> already hazard-free (unless the mapper decides to reimplement it,
>> which seems unlikely).
>
>Hazard-free as long as the set and reset pulses
>are well formed and far enough apart in time.
>It's not difficult to make an oscillation
>burst otherwise.

Gabor's comment referred to, presumably, single-variable static
hazards, and the cross-coupled NAND is already covered for this.

Oscillation isn't relevant here, because you can't noramlly solve for
multi-variable dynamic hazards by adding terms. It's not difficult to
make almost any async circuit oscillate by changing more than one
input 'simultaneously'. That's why they're normally designed to allow
only one input to change at a time, and why F/Fs have setup and hold
requirements, for example. An SR latch has similar timing requirements
on its 2 inputs.

Rick

"Mike Treseler" <mike_treseler@comcast.net> schrieb im Newsbeitrag
news:38jpfiF5ou9etU1@individual.net...

> Hazard-free as long as the set and reset pulses
> are well formed and far enough apart in time.
> It's not difficult to make an oscillation
> burst otherwise.

After all, what is a RS-FF good for nowadays??

Regards
Falk

On Tue, 1 Mar 2005 23:57:21 +0100, "Falk Brunner"
<Falk.Brunner@gmx.de> wrote:

>
>"Mike Treseler" <mike_treseler@comcast.net> schrieb im Newsbeitrag
>news:38jpfiF5ou9etU1@individual.net...
>
>> Hazard-free as long as the set and reset pulses
>> are well formed and far enough apart in time.
>> It's not difficult to make an oscillation
>> burst otherwise.
>
>After all, what is a RS-FF good for nowadays??

The same things that it has always been good for. For a cost of 2
gates, it gives you a memory. It doesn't need a clock. It remembers an
event until you have time to deal with it. It's ideal for handshaking,
and for communicating between different clock domains. Can you name
any other digital circuit which is so versatile, at such a small cost?
Even if you ignore the 'cost', as you might do in an FPGA
implementation?

Rick

"Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag
news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com...

> >After all, what is a RS-FF good for nowadays??
>
> The same things that it has always been good for. For a cost of 2
> gates, it gives you a memory. It doesn't need a clock. It remembers an
> event until you have time to deal with it. It's ideal for handshaking,
> and for communicating between different clock domains. Can you name
> any other digital circuit which is so versatile, at such a small cost?
> Even if you ignore the 'cost', as you might do in an FPGA
> implementation?

Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always free. So
why asking for trouble and doing stone age handshakes when there are proven
solutions using standard methods (here, D-FlipFlops)? I wouldnt waste a
nanosecond thinking of RS-FlipFlops made of gates.

Regards
Falk

Falk Brunner wrote:
> "Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag
> news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com...
>
> > >After all, what is a RS-FF good for nowadays??
> >
> > The same things that it has always been good for. For a cost of 2
> > gates, it gives you a memory. It doesn't need a clock. It remembers
an
> > event until you have time to deal with it. It's ideal for
handshaking,
> > and for communicating between different clock domains. Can you name
> > any other digital circuit which is so versatile, at such a small
cost?
> > Even if you ignore the 'cost', as you might do in an FPGA
> > implementation?
>
> Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always
free. So
> why asking for trouble and doing stone age handshakes when there are
proven
> solutions using standard methods (here, D-FlipFlops)? I wouldnt waste
a
> nanosecond thinking of RS-FlipFlops made of gates.

Speaking of cost, is a LUT less costly than a flip-flop?  In Xilinx
Virtex parts, a LUT can be 16 flip-flops sometimes.  Besides if you
want both gate outputs from your cross-coupled NAND gates you need
2 LUTs.

Another thing to wonder about, is whether changing a single
LUT input creates the same output transition as with the implemented
gates.  For example if the output is the same for both states of the
switched input, a gate will never glitch, but will the LUT glitch?
This may depend on the implementation of the output multiplexer.

> 
> Regards
> Falk

"Gabor" <gabor@alacron.com> wrote in message news:<1109889767.823586.126100@z14g2000cwz.googlegroups.com>...
> Falk Brunner wrote:
> > "Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag
> > news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com...
> >
> > > >After all, what is a RS-FF good for nowadays??
> > >
> > > The same things that it has always been good for. For a cost of 2
> > > gates, it gives you a memory. It doesn't need a clock. It remembers
> an
> > > event until you have time to deal with it. It's ideal for
> handshaking,
> > > and for communicating between different clock domains. Can you name
> > > any other digital circuit which is so versatile, at such a small
> cost?
> > > Even if you ignore the 'cost', as you might do in an FPGA
> > > implementation?
> >
> > Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always
> free. So
> > why asking for trouble and doing stone age handshakes when there are
> proven
> > solutions using standard methods (here, D-FlipFlops)? I wouldnt waste
> a
> > nanosecond thinking of RS-FlipFlops made of gates.
> 
> Speaking of cost, is a LUT less costly than a flip-flop?  In Xilinx
> Virtex parts, a LUT can be 16 flip-flops sometimes.  Besides if you
> want both gate outputs from your cross-coupled NAND gates you need
> 2 LUTs.
> 
> Another thing to wonder about, is whether changing a single
> LUT input creates the same output transition as with the implemented
> gates.  For example if the output is the same for both states of the
> switched input, a gate will never glitch, but will the LUT glitch?
> This may depend on the implementation of the output multiplexer.
> 
> > 
> > Regards
> > Falk

Although this is not directly related to the current SR latches
discussion, let me expose a problem that forced me to define a VHDL
equivalent of the good old 7474 flip-flop made with NAND gates and a
set of KEEP attributes on the signals.

Although it may be questionable to do so, once you try to synthetize a
flip-flop with such an expression as "If Rising_Edge(Signal_In) Then
...", where Signal_In is not supposed to be a general clock at all,
the synthesis tool generally reserves a global clock chain and buffer
for just that purpose.

This may be a real problem if the number of times you want to do that
(because for instance you need to have a very quick reaction on the
rising edge of a signal) gets significant vs the number of available
GCLK nets and buffers.

Pardon me if I am presently missing a very simple way to tell the tool
"Please do not use one of your GCLK resources", but I am not a very
frequent user of VHDL and had no chance to go to any advanced seminar
of any kind.

A solution to that problem ?

Please answer if you are aware of some.