HELP!!! Interfacing Virtex-4 FPGA with SDR SDRAM

Hello ALL,

This is my second message :( I did not get answer for the first one, so
I am sending it again. My be it got lost somewhere in news-server, or
this is not the right NG to post this message. Any way, people here are
talking about FPGA and SDRAM adn this is my current problem.

I am having hard time designing the schematic to interface conventional
SDRAM chip to Virtex-4 FPGA. As a SDRAM we have selected Micron 256Mbit
part with 32 bit wide data bus. Both packages a BGA, Virtex-4 is FF-672
type, SDRAM is FBGA-90. Our chips is planned to be located about 5-10mm
(0.2-0.4 inches) from each other and the longest trace is suppose to be
about 2.0-2.5 inches. We are also planning to have data bus traces to
be as short as possible. First approximation gives about 1.3-1.5 inches
data bus traces. The trace impedance is planned to be about 53-55Ohms.
The interface is planned to run at 125MHz.

The memory we are going to use has conventional 3.3V interface. We are
planning to use DCI for all outputs in our design, i.e. control
signals, address bus, clock and clock enable signals. Doing simulation
we found that DCI does pretty good job for all these lines - there is
no overshot/undershot problems at all on all these lines. The only
problem is the data bus. Than signal originates from Virtex-4 FPGA
everything goes fine, because DCI still active for this direction,
everything becomes bad when signal originates from SDRAM. There is
significant overshot and undershot around every edge of the signal. Its
value goes as high as 4.2V for overshot and to -900mV for undershot.
This extreme condition lasts for 200-300 picoseconds according to our
simulation. For simulation we are using Virtex-4 and SDRAM Ibis models
from manufacturers.

The relatively simple solution is to terminate each line in data bus,
but it requires relatively lots of space on the PCB and can not be done
reliably :( As soon as Micron driver gets terminated properly the line
becomes less than suitable for Virtex-4 driver, something in between is
not very good for both of them.

The funniest thing that I saw several existing and reliably working
designs, using average trace length about 2.5 inches with similar
components working with close frequencies and DOES NOT using any series
termination on data lines with default FPGA drivers. So, what part are
we missing? Should we believe in simulation or it is not as accurate as
expected?

With best regards, 
Vladimir S. Mirgorodsky

Validimir,

I don't believe you'll do any damage to the Virtex with the size
and duration of overshoot you have in your simulation.  I am not
yet using Virtex 4, but in all instances where I used SDR SDRAMs
I have not used DCI in the FPGA or installed series resistors.  Note
that the data bus is not a clock, so you have a lot of settling
time at 125 MHz to deal with overshoot and ringing.  Also be aware that
using DCI on a wide data bus can add significant power consumption.

The very short duration of the overshoot leads me to believe there is
very little power dissipated in the clamp diodes, and the relatively
high voltage during that time is most likely indicating turn-on
characteristics of the diode rather than showing large currents.  If
your simulation shows the data within the normal logic high or low
ranges by the time your FPGA samples it (clock edge minus setup time)
you should not have a problem with this design.

Regards,
Gabor

v_mirgorodsky@yahoo.com wrote:
> Hello ALL,
>
> This is my second message :( I did not get answer for the first one,
so
> I am sending it again. My be it got lost somewhere in news-server, or
> this is not the right NG to post this message. Any way, people here
are
> talking about FPGA and SDRAM adn this is my current problem.
>
> I am having hard time designing the schematic to interface
conventional
> SDRAM chip to Virtex-4 FPGA. As a SDRAM we have selected Micron
256Mbit
> part with 32 bit wide data bus. Both packages a BGA, Virtex-4 is
FF-672
> type, SDRAM is FBGA-90. Our chips is planned to be located about
5-10mm
> (0.2-0.4 inches) from each other and the longest trace is suppose to
be
> about 2.0-2.5 inches. We are also planning to have data bus traces to
> be as short as possible. First approximation gives about 1.3-1.5
inches
> data bus traces. The trace impedance is planned to be about
53-55Ohms.
> The interface is planned to run at 125MHz.
>
> The memory we are going to use has conventional 3.3V interface. We
are
> planning to use DCI for all outputs in our design, i.e. control
> signals, address bus, clock and clock enable signals. Doing
simulation
> we found that DCI does pretty good job for all these lines - there is
> no overshot/undershot problems at all on all these lines. The only
> problem is the data bus. Than signal originates from Virtex-4 FPGA
> everything goes fine, because DCI still active for this direction,
> everything becomes bad when signal originates from SDRAM. There is
> significant overshot and undershot around every edge of the signal.
Its
> value goes as high as 4.2V for overshot and to -900mV for undershot.
> This extreme condition lasts for 200-300 picoseconds according to our
> simulation. For simulation we are using Virtex-4 and SDRAM Ibis
models
> from manufacturers.
>
> The relatively simple solution is to terminate each line in data bus,
> but it requires relatively lots of space on the PCB and can not be
done
> reliably :( As soon as Micron driver gets terminated properly the
line
> becomes less than suitable for Virtex-4 driver, something in between
is
> not very good for both of them.
>
> The funniest thing that I saw several existing and reliably working
> designs, using average trace length about 2.5 inches with similar
> components working with close frequencies and DOES NOT using any
series
> termination on data lines with default FPGA drivers. So, what part
are
> we missing? Should we believe in simulation or it is not as accurate
as
> expected?
> 
> With best regards, 
> Vladimir S. Mirgorodsky