Asynchronous processor !?!

"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message 
news:PGtXd.744$n33.40@newsfe4-gui.ntli.net...

>
> I get the feeling things will have to go asynch eventually, if only to get 
> rid of a 40W RF transistor thrashing a global clock network.
>
The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz. 

"Pete Fraser" <pfraser@covad.net> wrote in message 
news:112ssmdbnlbe11e@news.supernews.com...

> The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz.

Crikey. Do tell more!


Regarding CPUs, I think there is much more scope for efficiency.
Even without moving to asynch CPUs.

As I type this on my laptop, the fan is still blowing.


A friend of mine knows the Psion very well, and says it spends almost all 
its time asleep waiting for events to wake it up - eg. keypresses.

On a PC, there is always a display controller accessing loads of pixel data.

Maybe that should be tackled first?

K.

As Jim says, for embedded apps, lower EMI, less heat are good things to
do but for high perf Async design is IMHO a wasted effort.

This issue comes up every so often, some think async will cure the ills
of digital design, to show for its results there is very little. There
is one little company in San Diego IIRC that does async asics, even a
couple of pretty die shots on site, and there was the Amulet and a book
or two.

SInce as Peter/Xilinx keep saying the asic is dead and long live the
FPGA, we have to stick with global clocking, even more so for FPGA than
Asics for obvious reasons. Atleast with Asics you could hand craft
everything so you could justify any clocking, power management scheme
to get the job done

Also look at the EDA world, name a single async tool vendor out there.

Also consider that par busses are dying and getting replaced by the
fastest possible serial busses, its one thing to do async sub clock
busses, can't see how you could do PCIe, Sata, FW, USB2/3 in a async
world.


I f that damn Moore guy hadn't had that "double every 18months" comment
we might still be exploring 1ucmos design space and then async design
actually would have a place to shine but we're are in a geometry rat
race and async lost its chance  to make any real show.

just my 2c

regards

johnjakson at usa dot com

"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message
news:2fvXd.6$ox4.2@newsfe4-gui.ntli.net...
>
> "Pete Fraser" <pfraser@covad.net> wrote in message
> news:112ssmdbnlbe11e@news.supernews.com...
>
>> The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz.
>
> Crikey. Do tell more!

My memory of it is slightly hazy (I didn't design it, I only used it.)

It used 1024 bit dynamic shift registers, which had a
multi-phase clock. The clock had a swing of something
like 16 or 20 volts, and had quite strict (fast) risetime
requirements into a rather large input capacitance.

We never measured the current, but doing the calculations
with voltage, risetime, and typical input capacitance gave
a peak clock current of 60 Amps. The r.m.s. was clearly much less.

I just did a quick google,and found a paper on it:

http://www.bbc.co.uk/rd/pubs/reports/1977-09.pdf

If I understand it correctly I was off by a factor of eight;
the current was closer to 500 Amps peak.