Surge in S2? ~3 amperes at cold for a millisecond

All,

I promised I'd get back with a scope picture on S2 power on surge on Vccint.

Since I don't get to post graphics here, I will have to ask those 
interested to get with their Xilinx FAE to get a scope shot.

If you email me directly, I can send it also (but I might be spammed to 
death buy the requests .... but I will honor them if they are not too many).

Basically, the 2S60 (that I tested) has between a 3/4 ampere, and three 
ampere surge for a millisecond or less with a 20 ms ramp on time.

Power supply sequence doesn't matter.  Temperature at cold is worse than 
temperature at hot, but I have but one part, so I have no idea how that 
holds of process.

No surges on any other supply.

The leakage follows the spreadsheet, that is there is a lot of 
Iccint(leak) at hot (about one ampere at 70C).  In fact, by specifying 
the "turn-on" current required for hot, they are probably able to ignore 
the 3 amperes at cold (eg -- if the start up current is equal to or less 
than the surge, then they can be honest and claim there is no surge).

I will accept that I may have an early version of silicon, and that Paul 
L. correctly stated that what I have seen is fixed in future 
tapeouts/silicon, but that remains to be seen as well.  Perhaps someone 
with a production device can confirm this is fixed?

Austin

"Current at cold is worse than current at hot" -- for the surge.

Spelled correctly, making nonsense.

Apologize for the minor goof.

Austin

Austin Lesea wrote:

> All,
> 
> I promised I'd get back with a scope picture on S2 power on surge on 
> Vccint.
> 
> Since I don't get to post graphics here, I will have to ask those 
> interested to get with their Xilinx FAE to get a scope shot.
> 
> If you email me directly, I can send it also (but I might be spammed to 
> death buy the requests .... but I will honor them if they are not too 
> many).
> 
> Basically, the 2S60 (that I tested) has between a 3/4 ampere, and three 
> ampere surge for a millisecond or less with a 20 ms ramp on time.
> 
> Power supply sequence doesn't matter.  Temperature at cold is worse than 
> temperature at hot, but I have but one part, so I have no idea how that 
> holds of process.
> 
> No surges on any other supply.
> 
> The leakage follows the spreadsheet, that is there is a lot of 
> Iccint(leak) at hot (about one ampere at 70C).  In fact, by specifying 
> the "turn-on" current required for hot, they are probably able to ignore 
> the 3 amperes at cold (eg -- if the start up current is equal to or less 
> than the surge, then they can be honest and claim there is no surge).
> 
> I will accept that I may have an early version of silicon, and that Paul 
> L. correctly stated that what I have seen is fixed in future 
> tapeouts/silicon, but that remains to be seen as well.  Perhaps someone 
> with a production device can confirm this is fixed?
> 
> Austin

Austin Lesea wrote:
> All,
> 
> I promised I'd get back with a scope picture on S2 power on surge on 
> Vccint.
> 
> Since I don't get to post graphics here, I will have to ask those 
> interested to get with their Xilinx FAE to get a scope shot.
> 
> If you email me directly, I can send it also (but I might be spammed to 
> death buy the requests .... but I will honor them if they are not too 
> many).

You could give a web link ? [less work for everyone ?]

-jg

Jim,

I am sure I can do that, but I have to go through marketing.  That will 
take awhile.  And then, marketing will want to put there imprimatur on it.

I'd prefer to keep it in this forum to give Paula chance to reply (as I 
said, I may have early silicon, whose masks may have been modified to 
fix this behavior).

Austin



Jim Granville wrote:
> Austin Lesea wrote:
> 
>> All,
>>
>> I promised I'd get back with a scope picture on S2 power on surge on 
>> Vccint.
>>
>> Since I don't get to post graphics here, I will have to ask those 
>> interested to get with their Xilinx FAE to get a scope shot.
>>
>> If you email me directly, I can send it also (but I might be spammed 
>> to death buy the requests .... but I will honor them if they are not 
>> too many).
> 
> 
> You could give a web link ? [less work for everyone ?]
> 
> -jg
> 

Well, I think there is a difference here.
On the newsgroup we can say:
"Altera Stratix-2 still has the infamous start-up current, even >2A on
a 2S60, and we have measurements to prove it".

But I am not too excited about honoring them with a Xilinx website,
only to have Altera then come back and claim that they finally "have
REALLY" fixed it.

Gentlemen should have some constraint in washing each other's dirty
laundry in public, or call each other "liar" in public, even when it
would be justified, as it is in this case.

I prefer the attitude that
"I am #1, and certain things are below my dignity. Let the other guy
crawl around in the mud, if he enjoys that environment".
But the newsgroup is like a club, where we can be more outspoken and
candid...
Peter Alfke

Hi Austin,

As I previously indicated, the EP2S60 *ES* (Engineering Sample) does
exhibit a surge current.  This current does not exist in any other
shipping SII device including the EP2S15, EP2S30, EP2S90ES, EP2S130,
and EP2S180.  The production EP2S60 devices, shipping later this month,
also do not exhibit a surge.

The surge current issue was reflected in the Early Power Estimator 2.0.
 Since it was fixed, it was removed in EPE 2.1.  We just realized that
the errata sheet for the ES device is missing this spec; this will be
rectified shortly.

> The leakage follows the spreadsheet, that is there is a lot of
> Iccint(leak) at hot (about one ampere at 70C).  In fact, by
specifying
> the "turn-on" current required for hot, they are probably able to
ignore
> the 3 amperes at cold (eg -- if the start up current is equal to or
less
> than the surge, then they can be honest and claim there is no surge).

The production start-up current is less than the operating (static)
current across all temperatures.

Incidentally, our ES devices exhibit higher-than-typical static
currents.  I noticed in the screenshot of our chip in your power
seminar that you were measuring an ES device, a fact you decided not to
mention in the talk...

> Perhaps someone
> with a production device can confirm this is fixed?

Austin, we have measured a bunch of production devices across process
corners, voltages, temperatures, different ramp rates, different power
supply start-up conditions, and on different days of the week for good
measure.  There is no contention-based start-up current.

Please, question our marketing all you want.  But our specs are our
specs.  Do not accuse us of lying.

Paul Leventis
Altera Corp.

Paul,

As I said, I wanted to give you the option to respond.

Thank you for clarifying when the new material that has been fixed will 
be available for the 2S60, and publishing an erratum for it.

I suppose it would do no good to ask for a replacement with production 
silicon?

As for webinar, is the leakage going to be less for all future 
production parts?  Sounds like the first ES lot was leakier because it 
was fast corner material.  It is possible that it was outside the wafer 
acceptance critera, so I will grant you that one, too.

This ES part was within the latest spreadsheet 'maximum' specifications.

'Typical' is not something you can design to in this case.

It would be unusual not to ship material that was a bit too fast, but I 
grant you that if you have a hot leakage test, you could scrap these in 
wafer sort, and customers would never see them.

Austin



Paul Leventis wrote:
> Hi Austin,
> 
> As I previously indicated, the EP2S60 *ES* (Engineering Sample) does
> exhibit a surge current.  This current does not exist in any other
> shipping SII device including the EP2S15, EP2S30, EP2S90ES, EP2S130,
> and EP2S180.  The production EP2S60 devices, shipping later this month,
> also do not exhibit a surge.
> 
> The surge current issue was reflected in the Early Power Estimator 2.0.
>  Since it was fixed, it was removed in EPE 2.1.  We just realized that
> the errata sheet for the ES device is missing this spec; this will be
> rectified shortly.
> 
> 
>>The leakage follows the spreadsheet, that is there is a lot of
>>Iccint(leak) at hot (about one ampere at 70C).  In fact, by
> 
> specifying
> 
>>the "turn-on" current required for hot, they are probably able to
> 
> ignore
> 
>>the 3 amperes at cold (eg -- if the start up current is equal to or
> 
> less
> 
>>than the surge, then they can be honest and claim there is no surge).
> 
> 
> The production start-up current is less than the operating (static)
> current across all temperatures.
> 
> Incidentally, our ES devices exhibit higher-than-typical static
> currents.  I noticed in the screenshot of our chip in your power
> seminar that you were measuring an ES device, a fact you decided not to
> mention in the talk...
> 
> 
>>Perhaps someone
>>with a production device can confirm this is fixed?
> 
> 
> Austin, we have measured a bunch of production devices across process
> corners, voltages, temperatures, different ramp rates, different power
> supply start-up conditions, and on different days of the week for good
> measure.  There is no contention-based start-up current.
> 
> Please, question our marketing all you want.  But our specs are our
> specs.  Do not accuse us of lying.
> 
> Paul Leventis
> Altera Corp.
> 

Hi Austin,

> As for webinar, is the leakage going to be less for all future production 
> parts?  Sounds like the first ES lot was leakier because it was fast 
> corner material.  It is possible that it was outside the wafer acceptance 
> critera, so I will grant you that one, too.

Most ES units while leakier than typical are still within (the now reduced) 
production specs.  Over time we gain better control over the process and 
hence can provide a better upper bound on worst-case leakage for production 
units.  This was reflected in the last spec upgrade.

> 'Typical' is not something you can design to in this case.

You don't need to convince me that looking at "typical" numbers for leakage 
is incorrect for most designs.  Altera has published worst-case Stratix II 
leakage specs since day one.

Paul Leventis
Altera Corp.

Peter Alfke wrote:

> But I am not too excited about honoring them with a Xilinx website,
> only to have Altera then come back and claim that they finally "have
> REALLY" fixed it.
[...]
> But the newsgroup is like a club, where we can be more outspoken and
> candid...

But Austin could post the images on a webpage and link to them in a 
newsgroup message.
I think a good place for such images would be fpga-faq.com but I could 
also place them on fpga.de

Kolja Sulimma

Er, Peter,

> Well, I think there is a difference here.
> On the newsgroup we can say:
> "Altera Stratix-2 still has the infamous start-up current, even >2A on
> a 2S60, and we have measurements to prove it".
> 
> But I am not too excited about honoring them with a Xilinx website,
> only to have Altera then come back and claim that they finally "have
> REALLY" fixed it.
> 
> Gentlemen should have some constraint in washing each other's dirty
> laundry in public, or call each other "liar" in public, even when it
> would be justified, as it is in this case.

Ok. In the same vein, what are you going to do about that slow interconnect
in the V4 series then?

Paul never called Austin a liar. He merely exposed a few unmentioned facts
in Austin's diatribe.

The EP2S60ES silicon is/was a power hog (ha, you should have heard the
raspberries when the ES power requirements were first mentioned to the
FAEs), and Altera has been exceedingly candid about this to all customers. 

For the EP2S60, ES silicon is all you'll find at the moment, and it would
have been better for your future credibility if Austin had immediately
mentioned that your measurements had indeed been done on an EP2S60ES.
Altera would have simply responded with "Yep, that's what we said. Didn't
you believe us?".

Then again, the world would have missed an interesting Usenet thread...

Best regards,



Ben