Hierarchical Synchronous Design

valentin tihomirov wrote:

> I think the OP asked for a proper design demo on the single signal path
> example.

The OP asked:

 > My question is if I use your advice, I would be registering 'OUT' at
 > each level, is that what I should do?

The consensus of the replies was, yes
if all else is equal, registering the outputs
of all design entities (modules) is a good thing.

Yes, I passed on a 5 level hierarchy example.
I prefer a two level hierarchy where the
the top level contains only instances
and wires. This eliminates the concern
about how a level 5 output escapes to the top.

         -- Mike Treseler