Good, affordable verilog simulator

Can anybody recommend a good PC-based verilog simulator for substantially less than $4500?

I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog source files. Mentor Graphics will not allow an inexpensive license switch from our present VHDL to the verilog (They charge full price and give us no credit for the previous full price purchase). I can't use the "Xilinx Edition ModelSim" becuase it won't support my target, the XC2VP20, as far as I know.

Any suggestions would be appreciated.

Paul Taddonio <paul.taddonio@futureplus.com> wrote:
> Can anybody recommend a good PC-based verilog simulator for substantially 
> less than $4500?

> I am a new hire at a company which spent big bucks on ModelSim just ...

First: put a line break at 60 charaters per line

> Any suggestions would be appreciated.

www.pragmatic-c.com
www.icarus.com/eda/verilog
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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just a guess,  try checking out active HDL.

Neo wrote:
> just a guess,  try checking out active HDL.

Last price list shows definitely more than 4,500 for Verilog-only
Active-HDL PE.  I don't know if they will separate the simulator
from the development environment.

Gabor wrote:
> Neo wrote:
> 
>>just a guess,  try checking out active HDL.
> 
> 
> Last price list shows definitely more than 4,500 for Verilog-only
> Active-HDL PE.  I don't know if they will separate the simulator
> from the development environment.
> 
Maybe you should ask them for Riviera instead of Active-HDL?

Regards,
PR

You can get a VHDL netlist post-synthesis (depending upon the 
synthesizer you are using), post-NGD build, post-map, or post-PAR. 
Debugging your RTL from a post-NGD build VHDL netlist might not be as 
easy as debugging a Verilog RTL sim, but it may be your best option and 
requires no more cash.  See the help for the Xilinx executable 'netgen' 
for details on creating VHDL netlists from NGD or NCD files. -Kevin

Paul Taddonio wrote:
> Can anybody recommend a good PC-based verilog simulator for substantially less than $4500?
> 
> I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog source files. Mentor Graphics will not allow an inexpensive license switch from our present VHDL to the verilog (They charge full price and give us no credit for the previous full price purchase). I can't use the "Xilinx Edition ModelSim" becuase it won't support my target, the XC2VP20, as far as I know.
> 
> Any suggestions would be appreciated.

Try GPL Cver, it's 1394 compliant and it's free.

http://www.pragmatic-c.com/gpl-cver/

Kevin, I wouldn't mind simulating in VHDL, but the Xilinx tool won't let me setup any of the "create simulation model" processes to output VHDL. I only get a variety of verilog flavors to choose from. (My source files are verilog.) Do you know a different way?

OK, I found the documentation on NetGen. I'll give it a try. Thanks everyone for responding.

Paul Taddonio wrote:
>We have a tight schedule so I will stick with the familiar language. 
>Any suggestions would be appreciated.

Going from Verilog to VHDL isn't as big a headache as you think.
Go to http://www.confluent.org/wiki/doku.php and click on HDL comparison 
to get a quick guide on the differences in Confluence, Verilog and VHDL.