Global Reset paths

A Beaujean wrote:

> OK. Well, there follows a link with a very interesting paper on
> potential problems with (too) simple asynchronous resets.
> 
> http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
> 
> Having acknowledged the potential dangers described in that paper, I
> now systematically create for my VHDL designs a synced reset per clock
> domain and uses those synced resets as async reset inputs on all
> registers of the design. I just let the synthesis and PAR tool operate
> as usual, giving no special directive, and got not problem until now.

Hi Beaujean,

do the registers which are used to sync the external reset
have an asynchronous reset input ? If yes, what signal does feed these 
reset inputs ?


Thanks for all posts.

Best Rgds
Andr�s

Andr&#4294967295;s <nospam_nussspucke@gmx.de> wrote in message news:<39lghjF62701cU1@individual.net>...
> A Beaujean wrote:
> 
> > OK. Well, there follows a link with a very interesting paper on
> > potential problems with (too) simple asynchronous resets.
> > 
> > http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
> > 
> > Having acknowledged the potential dangers described in that paper, I
> > now systematically create for my VHDL designs a synced reset per clock
> > domain and uses those synced resets as async reset inputs on all
> > registers of the design. I just let the synthesis and PAR tool operate
> > as usual, giving no special directive, and got not problem until now.
> 
> Hi Beaujean,
> 
> do the registers which are used to sync the external reset
> have an asynchronous reset input ? If yes, what signal does feed these 
> reset inputs ?
> 
> 
> Thanks for all posts.
> 
> Best Rgds
> Andr&#4294967295;s

The setups for the two flip-flops used are very well described in the
paper mentioned :
 http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
 on pages 21 and 22 (page 22 gives a VHDL implementation).

The form I used in VHDL is very slightly different, but strictly
equivalent in terms of functionality.

Architecture Arch_Of_SAFE_ASYNC_RESET Of SAFE_ASYNC_RESET Is
--
-- Signals
--
Signal First_Ff      : std_logic ;
--
Begin
--
-------------------------------------------------------------------------------
--
--                          SYNCHRONOUS PROCESSES 
--
-------------------------------------------------------------------------------
--
First_Ff_Process:
Process(Reset_Not_In,Clock)
Begin
If (Reset_Not_In = '0') Then
  First_Ff <= '0' ; 
                        Else
  If Rising_Edge(Clock) Then
    First_Ff <= '1' ;
  End If ;
End If ;
End Process ;
--
Reset_Not_Out_Process:
Process(Reset_Not_In,Clock)
Begin
If (Reset_Not_In = '0') Then
  Reset_Not_Out <= '0' ; 
                        Else
  If Rising_Edge(Clock) Then
    Reset_Not_Out <= First_Ff ;
  End If ;
End If ;
End Process ;
--
End Arch_Of_SAFE_ASYNC_RESET ;

Hope this serves a bit.

A. Beaujean