Verilog-2001 and Xilinx ISE 7.1?

When I tried Xilinx Webpack 6.3, I noticed that the XST (Xilinx
Synthesis Technology) was missing some Verilog-2001 features.

For me, the showstoppers were no $signed and $unsigned system-
tasks.  (I know they don't do anything when moving between
signed<->unsigned vectors of identical bit-width, but our RTL
uses them to clearly denote the designer's intent.)

And lack of Verilog macro-arguments ...

`define MINIMUM2( x , y )   ( ((x) < (y)) ? (x) : (y) )

^^^ This causes XST preprocessor to throw a syntax-error.

Have these issues been addressed?