Virtex 4 USER1 ~ USER4 JTAG commands

Hello everyone,

I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~
USER4 JTAG commands from my software.

I have used my software to access such USER1, USER2 commands in
previous generation FPGAs such as Virtex-II.

Virtex 4 uses different JTAG command bit patterns (10 bit long) and I
changed the table so that JTAG commands to be issued have the correct
JTAG command bit patterns.

Anyway, after spending hours and hours, I couldn't make it working. The
JTAG command sequence seems correct as far as I see in the scope and
HEX print out. Also, I can get the correct IDCODE using JTAG IDCODE
command.

IDCODE = 10'b1111001001
USER1  = 10'b1111000010

I added probes to BSCAN module signals so that I could see the signals
coming out from the BSCAN module. But I didn't see any signals coming
out from the BSCAN module even I tried all USER1 ~ USER4 commands. (ex.
sendIR(USER1) + readDR())

My question is "Does anybody try using the Virtex4 USERx JTAG command?"

If anybody have tried it, I definitely would like to hear that.
I checked the Internet newsgroup as well as Xilinx support but so far,
I cannot find any relevant info regarding to this.

Any info, any suggestions would be highly appreciated.

Best regards,
Aki Niimura

read the ERRATA !!!

V4 ES silicon only has USER1 command USER2,3,4 are not working at all.

Antti
PS the USER1 seems to work as the XMD and ChipScope both can communicate
over USER1




<akineko@gmail.com> schrieb im Newsbeitrag
news:1110446449.077000.311890@o13g2000cwo.googlegroups.com...
> Hello everyone,
>
> I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~
> USER4 JTAG commands from my software.
>
> I have used my software to access such USER1, USER2 commands in
> previous generation FPGAs such as Virtex-II.
>
> Virtex 4 uses different JTAG command bit patterns (10 bit long) and I
> changed the table so that JTAG commands to be issued have the correct
> JTAG command bit patterns.
>
> Anyway, after spending hours and hours, I couldn't make it working. The
> JTAG command sequence seems correct as far as I see in the scope and
> HEX print out. Also, I can get the correct IDCODE using JTAG IDCODE
> command.
>
> IDCODE = 10'b1111001001
> USER1  = 10'b1111000010
>
> I added probes to BSCAN module signals so that I could see the signals
> coming out from the BSCAN module. But I didn't see any signals coming
> out from the BSCAN module even I tried all USER1 ~ USER4 commands. (ex.
> sendIR(USER1) + readDR())
>
> My question is "Does anybody try using the Virtex4 USERx JTAG command?"
>
> If anybody have tried it, I definitely would like to hear that.
> I checked the Internet newsgroup as well as Xilinx support but so far,
> I cannot find any relevant info regarding to this.
>
> Any info, any suggestions would be highly appreciated.
>
> Best regards,
> Aki Niimura
>

> V4 ES silicon only has USER1 command USER2,3,4 are not working at
all.

Antti, you saved my day. I was actually using USER2 command and my
Virtex-4 is an ES part.

> read the ERRATA !!!

These day so many thing I need to read and everybody is using ERRATA to
justify the bugs they made (actually I do, too). But I should have been
more careful about such.

Anyway, thank you for your prompt response.

Best regards,
Aki Niimura

Antti Lukats wrote:
> read the ERRATA !!!
>
> V4 ES silicon only has USER1 command USER2,3,4 are not working at
all.
>

Additional info:
I found Xilinx Answer Record #20129 mentioning the problem in the
Virtex 4 LX25 ES part.

> General Description:
> LX25's BSCAN_VIRTEX4 RESET and DRCK signals might not function
> as expected on the ES parts.
>
> Solution 1:
>
> To work around this issue, simply invert the RESET output and
> avoid using DRCK signals when the JTAG_CHAIN attribute is set
> to other than "1". However, since this issue will be fixed
> in a future device revision, implementing this work-around
> might result in an incompatibility with this future revision.

//

In short, LX25's JTAG BSCAN block is broken (ES part). I painfully
found that the JTAG Reset signal polarity was inverted!


Hope other people won't stumble on this problem like me.

Aki-