Which HDL?

Hello,

I would like to start a serious adventure in FPGA development,
so which HDL would you recommend me? I can restrict myself
to a single chip vendor (i.e. Altera, because their chips are quite
cheap and very easy to obtain in small quantities in Poland),
thus the spectrum of alternatives should be wider. The most
important thing is good support of genericity, for instance:

    generic type vector{N} where {const N : positive} is group of N bits
    x : vector(32); -- x : std_logic_vector(31 downto 0)

or even constants:

    generic const square{N} : type of N where {const N} is N*N;
    const nine : int is square{3};

The languages I know about are:

VHDL: very disappointing, the nicest part of Ada has ben removed.
No support for anonymous types, stiff and annoying syntax, weak
interface inference (needs explicit component specifications).

Verilog: same as above + lack of generate statements, so how
does one specify generic pipelines (very useful e.g. in parallel
CORDIC specifications)?

AHDL: I don't know much about it, because I can't find a good manual.

    Best regards
    Piotr Wyderski

Apart from behavioral languages such as systemC thats about
it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best
bet,its not perfect but its better than a poke in the eye with a sharp
stick..

Hi

Jezwold wrote:
> Apart from behavioral languages such as systemC thats about
> it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best
> bet,its not perfect but its better than a poke in the eye with a sharp
> stick..

I agree.

If you want to implement the hardware I recomment either verilog or VHDL.
AHDL is vendor specific while most vendor tools can deal with both
verilog or vhdl or mixed.

So now between verilog and vhdl, I can hardly guide you. I don't know
verilog but from what I've seen it's more concise than VHDL. The latter
tends to be very verbose. However, I work only with vhdl and I'm happy,
with generate you can write more "generic" code to be reused and it
still syntetize well.

Finally, what ever you choose, never forget that you must decribe the
hardware you want built and not the behavior you want implemented !


	Sylvain

In article <d11kuf$ia5$1@news.dialog.net.pl>,
 "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> writes:

|> VHDL: very disappointing, the nicest part of Ada has ben removed.
|> No support for anonymous types, stiff and annoying syntax, weak
|> interface inference (needs explicit component specifications).

Hm, you can define components in packages and just "use" them. So you don't need
to cut'n'paste the interface into each architecture. A lot of VHDL examples
(esp. from the FPGA vendors) don't use packages, as it hides the port names and
makes the instantiation examples harder to understand.

-- 
         Georg Acher, acher@in.tum.de
         http://wwwbode.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias

Jezwold wrote:

> its not perfect but its better than a poke in the eye with a sharp
> stick..

Only *just*... ;)

Mark

Piotr Wyderski wrote:
> Hello,
>
> I would like to start a serious adventure in FPGA development,
> so which HDL would you recommend me? I can restrict myself
> to a single chip vendor (i.e. Altera, because their chips are quite
> cheap and very easy to obtain in small quantities in Poland),
> thus the spectrum of alternatives should be wider. The most
> important thing is good support of genericity, for instance:
>
>     generic type vector{N} where {const N : positive} is group of N
bits
>     x : vector(32); -- x : std_logic_vector(31 downto 0)
>
> or even constants:
>
>     generic const square{N} : type of N where {const N} is N*N;
>     const nine : int is square{3};
>
> The languages I know about are:
>
> VHDL: very disappointing, the nicest part of Ada has ben removed.
> No support for anonymous types, stiff and annoying syntax, weak
> interface inference (needs explicit component specifications).
>
> Verilog: same as above + lack of generate statements, so how
> does one specify generic pipelines (very useful e.g. in parallel
> CORDIC specifications)?
>

Verilog 2001 does support generate.  It also supports arrays of
instances which are often easier to use than generate for many
applications.  Verilog is also very popular in the U.S. although
it has fewer followers elsewhere.  If you already know VHDL the
more concise nature of Verilog may not be a big win, nor Verilog's
similarity to C.

Another thing to remember about Verilog is that it is less rigid
about type-checking.  For example you can build designs where the
size of a vector applied to a module port doesn't match the size
in the module.  This will only generate a warning - not an error,
and warnings are easy to miss when the tools produce 100's of them.

Just my 2 cents.

Gabor

> AHDL: I don't know much about it, because I can't find a good manual.
> 
>     Best regards
>     Piotr Wyderski

Jezwold wrote:
> Apart from behavioral languages such as systemC thats about
> it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best
> bet,its not perfect but its better than a poke in the eye with a sharp
> stick..
> 

I thought VHDL was a poke in the eye with a sharp stick :->

I find Verilog a heck of a lot easier and results in more compact code
vs. VHDL. Verilog-2001 seems to have what was missing between the last
version and VHDL (generate, configurations, good file I/O, lots of
other new stuff). AHDL was the easiest to write, but supported only by
Altera, therefore no coded testbenching.

-- Pete

Gabor wrote:

> Verilog 2001 does support generate.  It also supports arrays of
> instances which are often easier to use than generate for many
> applications. 

So I'll have a look at it.

> Another thing to remember about Verilog is that it is less rigid
> about type-checking.

Yes, this is a big disadvantage.

    Best regards
    Piotr Wyderski

Georg Acher wrote:

> Hm, you can define components in packages and just "use" them. So
> you don't need to cut'n'paste the interface into each architecture.

Thanks, I didn't know about that. Looks like one of my problems has been
solved.

    Best regards
    Piotr Wyderski