Stratix II vs Virtex 4

Hello everyone,

I have a rather high performance design that acts as a high through-put data
path with some DSP manipulation on the way through.

I had been rather certain that I was going to move through to production
using Stratix/Stratix II parts.  However, the other day I sat down with a
distributor who was able to point out some very interesting items for
comparisons with the V4 chips.

Here are the four main items brought up:

1) Faster RAM
2) Potentially Lower power consumption
3) Price-points in the $120-160 range
4) More flexibility on the parallel LVDS inputs to the chip

I'm interested to hear anyone with first hand comparisons between the V4 and
other chips.

Thanks,

Keith

Keith Williams wrote:
> Hello everyone,
>
> I have a rather high performance design that acts as a high
through-put data
> path with some DSP manipulation on the way through.
>
> I had been rather certain that I was going to move through to
production
> using Stratix/Stratix II parts.  However, the other day I sat down
with a
> distributor who was able to point out some very interesting items for
> comparisons with the V4 chips.
>
> Here are the four main items brought up:
>
> 1) Faster RAM
> 2) Potentially Lower power consumption
> 3) Price-points in the $120-160 range
> 4) More flexibility on the parallel LVDS inputs to the chip
>
> I'm interested to hear anyone with first hand comparisons between the
V4 and
> other chips.

Howdy Keith,

If you register the output of the BRAM, then yes, it's probably faster.
 Otherwise, probably not.  Do you need that much speed?  You didn't
really give any design info (target speeds, device/design size, etc).

There was a considerable "debate" on comp.arch.fpga last month about
the power differences between the S2 and V4, and while I am positive
that the Virtex-4 static power is lower, I am less convinced that when
a high speed design is running in the device that is well utilized, the
total power will be THAT much different between the two.  Device size
factors into the power equation as well.

In short, he _might_ be right on any or all accounts, but until you
actually have a price quote in your hand from each vendor for a
selected part, and target your design to get design speeds, and run the
power estimators for each, it is too close to call, IMO.

The ISERDES and OSERDES are quite neat features though, and when
combined with the no-brainer local routing and clock divider, may make
a compelling sell on its own.  

Good luck,

   Marc

Keith,

The power story is a very good one, and we have the data to prove it.

When the chip is actually operating (only time you would care), the 
junction temoerature is bound to increase.

Then the static power different really stands out (>2X improvement, 
worst case, typically 4X better).

The dynamic interconnect power for the two is equal.

Our dynamic BRAM power is half that in S2.  That can be a few watts in a 
DSP design.

The DSP48 when arranged to use the internal dedicated cascading paths 
has 1/8th the power of the S2 solution.

Bottom line:  a high, end fast DSP design may disspate half the power in 
V4 over S2.  And the junction temperature will be at least 15 degress 
lower (for equivalent heatsinks) making heatsinking or airflow less 
costly as well.

That is why we are taking previously "won" sockets away from S2 for G4 
basestations.  Heat is the #1 enemy of all wired and wireless network 
equipment, because heat means energy, and energy means more batteries, 
and less holdover time, and more air conditioning costs in the central 
office, and more failures in the field.

We also have the SX25, SX35, and SX55 which are optimized for DSP 
applications, to provide a lower cost part to get the same amount of DSP 
resources.  There is NO COMPETITION AT ALL from Altera here:  it DOESN'T 
EVEN EXIST.

Austin

I disagree with every claim in Austin's post, which may be a new record. 
Rather than debate them here in text form yet again, I'd encourage those 
interested in real power data and comparisons to attend the Power Net 
Seminar I'm presenting on Thursday, March 24 at 11 am Pacific Standard Time.

I'll be providing a lot of detailed power comparisons between Stratix II and 
Virtex 4, using both measured data and the published estimators and 
specifications of both companies.  As well, I'll provide a first look at 
HardCopy II power, and show you the power reductions you can expect from it.

To register (free of course), see 
http://www.altera.com/education/net_seminars/current/ns-fpgapower.html.

Hope to see you there,

Vaughn
[v b e t z (at) altera.com]