I'm trying to get a gigabit ethernet design to work with Xilinx's Gige MAC (gemac 5.0/pcs combination) through the rocket IOs/optical transcievers on the ML300 board. I have a simple little design which drives two of the ethernets and prints out received info for one of the ethernets to the screen. With a fibre between the two active ethernets, all is fine: The MGTs and the PCSs sync up within a short time (<1 second for most of the ethernets, one is weaker and seems to require 2-4 seconds to sync up, so I'm not using that ethernet), and once it syncs up, packets are sent without an issue. But with a fibre to the PC on my desk (an HP GigE 1000-SX adaptor), the MGT and PCS don't sync up, so naturally it can't send or receive packets. The PC is sending out pings at .01 seconds on the ethernet (verified by TCP dump), so it isn't just an idle link. One worry in particular I have is on the clocking: The ML300 uses a 125 MHz ethernet reference clock, but the RocketIO wants a 62.5 MHz clock. Additionally, the userclk1's rising edges (the 62.5 MHz clock for the receiver/sender logic path) must be aligned with the falling edges of userclk2 (the 125 MHz clock). Thus, the clocking is DLL (/2) -> userclk/refclk DLL (shift 180) -> userclk2 Since the rocketIO manual recommends direct from the crystal (NOT through the DLL), I'm worried about the refclk (eg, jitter) but have no other choice. Does anyone have any suggestions? I've got a mini GBIC module on order so I can hook the ML300 up to a switch as well. Does anyone have a working design using the gemac core (not the older gigabit mac with integrated PCS) on the ML300 I could use for testing? -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
ML300 Gigabit Ethernet Issues...
Started by ●March 22, 2005
Reply by ●March 22, 20052005-03-22
The resolution: The ML300 manual lies, and the errata sheet doesn't seem to exist. The crystal is 62.5 MHz on later ML300 boards, not 125 MHz. Paul Hartke told me that there was a change in the board type to have the 62.5 MHz crystal (to meet the RocketIO recommendations discussed in the previous post.). Looking on the crystal itself (component X101) revealed that I had a newer board with the slower crystal. Finding that out, and then changing the clocking of the design so 62.5 MHz (really) -> Refclk -> DLL -> userclk \x2 -> userclk2 And now all is happy, I can send between the board and PC. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu