clock division using DCM, how?

Hello to all of you,

currently I'm working on a "game of life" implementation on FPGA. 
Everything seems to work fine except for some pixel columns that are
giving strange results.
I'm quite convinced that the vhdl code, which you can find on my site
( http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm
) is correct.
So I assume the error is related to timing problems of some kind.  I'm
relatively new to the whole FPGA stuff and have to learn everything
myself, and timing and constraints is so complicated that I often
don't know where to start.
If you take a closer look at the VHDL code you can see that in the
vgacontroller entity a signal xclk is generated, this is just a 25MHz
signal, which is then used for a whole lot of synchronization.

I have read about the clock nets available on FPGA and found something
at http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf about DCM.  I
suppose there's a better way to doing things than mine, I just don't
really know how.

As a conclusion: how do I implement a clock on the "time net" with a
frequency which is one fourth (25 MHz) of the hardware provided
frequency (100 MHz)

Kind regards, Jef Patat