Hi folks, I'm trying to get a DDR-SDRAM controller work as an AHB slave. According to the transfer timings in the AMBA Spec. Rev. 2, the next transfer can't go on until the slave involved in the previous transfer sets the HREADY signal. That means each time a read transfer associated with the DDR is initiated, AHB masters have to wait until the DDR finishes the read burst and puts the read data on the bus, and even another read command involved with the same row as in the current read transfer is not allowed. I think that's really a waste in timing, and will lead to a low efficiency of the DDR bandwidth. Any solutions? regards, Kevin ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.net
DDR SDRAM interface working with AMBA-AHB
Started by ●March 24, 2005
Reply by ●March 24, 20052005-03-24
> Hi folks, > I'm trying to get a DDR-SDRAM controller work as an AHB slave. > According to the transfer timings in the AMBA Spec. Rev. 2, the next > transfer can't go on until the slave involved in the previous transfer > sets the HREADY signal. That means each time a read transfer associated > with the DDR is initiated, AHB masters have to wait until the DDR finishes > the read burst and puts the read data on the bus, and even another read > command involved with the same row as in the current read transfer is not > allowed. I think that's really a waste in timing, and will lead to a low > efficiency of the DDR bandwidth. > Any solutions? > regards, > KevinEuhm, consider doing 'smart' things like prefetch, data buffering,... I've implemented an AHB bridge to the Altera DDR-SDRAM controller and I'm achieving 92% of the bandwith in burst mode. Both read and write. So for a DDR333 CAS2.5 and 64 bit DDR I've got 2.4Gbytes/s. Jan