LVPECL, Virtex II and the EP445

I have a bank of On Semiconductor EP445 1:8 deserializer chips
operating at LVPECL levels.

The eight outputs are single-ended.

How does one bring a single-ended LVPECL signal into a Virtex II?

Using buffers to make them differential is out of the question. I have
64 of these signals.

"Quiet Desperation" <nospam@nospam.com> wrote in message
news:240320051704165633%nospam@nospam.com...
> I have a bank of On Semiconductor EP445 1:8 deserializer chips
> operating at LVPECL levels.
>
> The eight outputs are single-ended.
>
> How does one bring a single-ended LVPECL signal into a Virtex II?
>
> Using buffers to make them differential is out of the question. I have
> 64 of these signals.


First, the FPGA banks would need to be at 3.3V. Then, you could:

1) Use two FPGA inputs (P/N pairs) per LVPECL output. The N side of one of
the diff input pairs would be biased to the common-mode level of the LVPECL
output. The drawback of this is that it will take 128 FPGA input pins.

or

2) Use SSTL3 inputs and tie all the VREF pins to the bias point (the
common-mode level of the LVPECL outputs). This will reduce the total number
of FPGA input pins required.

Bob

In article <Y%K0e.3247$gI5.474@newsread1.news.pas.earthlink.net>, Bob
<nimby1_notspamm_@earthlink.net> wrote:

> "Quiet Desperation" <nospam@nospam.com> wrote in message
> news:240320051704165633%nospam@nospam.com...
> > I have a bank of On Semiconductor EP445 1:8 deserializer chips
> > operating at LVPECL levels.
> >
> > The eight outputs are single-ended.
> >
> > How does one bring a single-ended LVPECL signal into a Virtex II?
> >
> > Using buffers to make them differential is out of the question. I have
> > 64 of these signals.
> 
> 
> First, the FPGA banks would need to be at 3.3V. Then, you could:
> 
> 1) Use two FPGA inputs (P/N pairs) per LVPECL output. The N side of one of
> the diff input pairs would be biased to the common-mode level of the LVPECL
> output. The drawback of this is that it will take 128 FPGA input pins.
> 
> or
> 
> 2) Use SSTL3 inputs and tie all the VREF pins to the bias point (the
> common-mode level of the LVPECL outputs). This will reduce the total number
> of FPGA input pins required.
> 
> Bob

Eewww... Thanks for the info, though. I'll ponder these two. The 128
inputs is fine because if there were a version of the 445 with
differental outputs, I'd buy it. My resistance to using buffers to make
them differential was the number of external buffers I would need.

The SSTL3 is an intersting idea.

Quiet Desperation wrote:
> I have a bank of On Semiconductor EP445 1:8 deserializer chips
> operating at LVPECL levels.
>
> The eight outputs are single-ended.
>
> How does one bring a single-ended LVPECL signal into a Virtex II?
>
> Using buffers to make them differential is out of the question. I
have
> 64 of these signals.

Howdy,

That is a bit of a toughie.  Spec's for the EP445:

Voh is between 2155 and 2540 mV.
Vol is between 1355 and 1740 mV.
Min Swing ~800 mV, although typical looks to be closer to 850 or
higher.

Looks like the output is normally centered around ~1950 mV, although
spec shows it could be as low as 1790 or as high as 2115.

As you probably know, this doesn't match up with any of the "normal"
standards.  I'll bet you could abuse the GTLP or single-ended SSTL or
HSTL modes to get the job done by adjusting the vref and vcco values up
to the values you need for this, although all of those standards have
very small hysteresis.

So you might be able to get away with AC-coupling the signals and
re-biasing them, in which case not only could you perhaps use the above
input types, but also maybe a PCI or LVCMOS1_n input type?

Or as Bob posted, you could go ahead and chew up 2x the number of pins
and bias the _n input of a differential receiver to the mid-point.

Good luck,

  Marc

Marc Randolph wrote:

>Quiet Desperation wrote:
>  
>
>>I have a bank of On Semiconductor EP445 1:8 deserializer chips
>>operating at LVPECL levels.
>>
>>The eight outputs are single-ended.
>>
>>How does one bring a single-ended LVPECL signal into a Virtex II?
>>
>>Using buffers to make them differential is out of the question. I
>>    
>>
>have
>  
>
>>64 of these signals.
>>    
>>
>
>Howdy,
>
>That is a bit of a toughie.  Spec's for the EP445:
>
>Voh is between 2155 and 2540 mV.
>Vol is between 1355 and 1740 mV.
>Min Swing ~800 mV, although typical looks to be closer to 850 or
>higher.
>
>Looks like the output is normally centered around ~1950 mV, although
>spec shows it could be as low as 1790 or as high as 2115.
>
>  
>
For this you have the VBB output on single ended ECL devices.  Indeed 
3.3V SSTL has the highest
VREF and should suit best with one EP445 connected to one IO-bank with 
VBB connected to
VREF. I once saw an app note were they used resistor dividers to get 
from PECL to LVDS.
This could be done either to accomplish true SSTL levels but might 
degrate speed.
One might just have a look ar 
http://www.onsemi.com/pub/Collateral/AND8066-D.PDF

>As you probably know, this doesn't match up with any of the "normal"
>standards.  I'll bet you could abuse the GTLP or single-ended SSTL or
>HSTL modes to get the job done by adjusting the vref and vcco values up
>to the values you need for this, although all of those standards have
>very small hysteresis.
>
>  
>
That's no problem as long as your VREF is ok.

>So you might be able to get away with AC-coupling the signals and
>re-biasing them, in which case not only could you perhaps use the above
>input types, but also maybe a PCI or LVCMOS1_n input type?
>
>  
>
 From performance point of view this is best if voltage translation is 
required, but requires DC balanced
data patterns.

>Or as Bob posted, you could go ahead and chew up 2x the number of pins
>and bias the _n input of a differential receiver to the mid-point.
>
>  
>
The advantage of using seperate VREF pins (that's basicly what you are 
doing) could be that
the IO bank restriction falls. But even on parts with high IO count 
banking shouldn't be a problem.
I'd prefer single ended connections (from the EP445) from the PCBs point 
of view.

Regards
Thomas

In article <1111722059.509960.148040@z14g2000cwz.googlegroups.com>,
Marc Randolph <mrand@my-deja.com> wrote:

> Or as Bob posted, you could go ahead and chew up 2x the number of pins
> and bias the _n input of a differential receiver to the mid-point.

This is probably best as I was prepared to do that anyway in the
parallel univered where On Semi made the outputs of the 445
differential. ;-) It's an XC2V4000 in a BF957 package. It's the 64
signals in and then another 64 out on the far side. That's 90% of this
chip's I/O. The rest is just control lines and a serial data link from
another FPGA.

Thanks for the tips, guys.

Quiet Desperation wrote:
> In article <1111722059.509960.148040@z14g2000cwz.googlegroups.com>,
> Marc Randolph <mrand@my-deja.com> wrote:
>
> > Or as Bob posted, you could go ahead and chew up 2x the number of
pins
> > and bias the _n input of a differential receiver to the mid-point.
>
> This is probably best as I was prepared to do that anyway in the
> parallel univered where On Semi made the outputs of the 445
> differential. ;-) It's an XC2V4000 in a BF957 package. It's the 64
> signals in and then another 64 out on the far side. That's 90% of
this
> chip's I/O. The rest is just control lines and a serial data link
from
> another FPGA.

Reminds me of a new 4VFX60 design that we've started... 40 general
purpose I/O pins (all CPU and clock related) + some RocketIO channels.
The ideal package to allow movement to a larger device if neccessary,
would be the FF1152 pkg.  Talk about having a few unused pins!

Have fun,

   Marc

> Marc Randolph <mrand@my-deja.com> wrote:
>
> This is probably best as I was prepared to do that anyway in the
> parallel univered where On Semi made the outputs of the 445
> differential.

I haven't used any of them recently, but I think there are several
1-10 Gbps shift register/demux parts with diff. outputs available,
from the other usual suspects ( Micrel/Vitesse/Maxim/etc. )

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1432/ln/
http://www.rsc.rockwell.com/highspeed/files/PB_0030XA0-1103.pdf

Brian

In article <1111782597.058021.232490@z14g2000cwz.googlegroups.com>,
Brian Davis <brimdavis@aol.com> wrote:

> I haven't used any of them recently, but I think there are several
> 1-10 Gbps shift register/demux parts with diff. outputs available,
> from the other usual suspects ( Micrel/Vitesse/Maxim/etc. )

Yeah, looked through all those before settling on the EP445. A lot of
those are either overkill for my input, only 1:4 or they're really only
good for SONET rates. 

What I want is a programmable 1:N and N:1 serializer, deserializer pair
of chips with N = 2 to 16.

Quiet Desperation wrote:
> In article <1111782597.058021.232490@z14g2000cwz.googlegroups.com>,
> Brian Davis <brimdavis@aol.com> wrote:
>
> > I haven't used any of them recently, but I think there are several
> > 1-10 Gbps shift register/demux parts with diff. outputs available,
> > from the other usual suspects ( Micrel/Vitesse/Maxim/etc. )
>
> Yeah, looked through all those before settling on the EP445. A lot of
> those are either overkill for my input, only 1:4 or they're really
only
> good for SONET rates.
>
> What I want is a programmable 1:N and N:1 serializer, deserializer
pair
> of chips with N = 2 to 16.

For what data-rate(s)?

   Marc