Hi first - I am a very Xilinx biased (possible because I have way more Xilinx boards) but the latest Quartus seems really easy and in some cases better than X tools (at least the built in programmer is FASTER to use than impact) Story: After getting a nice application tested on Xilinx FPGA I just out of curiosity tried to port to Altera devices, the only problem I had was related to lack of documentation on the cyclone_jtag and maxii_jtag, after solving those the original xilinx code compiled without changes and worked too :) http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter after first success with Cyclone, I tried it on MAX2 and worked again :) MAX2 is really nice well its not so much an PLD but more like Xilinx XC2K reinvented and made flash based ;) anyway it is really a heavy player on the flash device arena as the other suppliers Atmel and Lattice are not yet shipping their low-cost flash FPGAs Antti
some +. for Altera
Started by ●March 26, 2005
Reply by ●March 26, 20052005-03-26
Hi Antti, At ALSE, we design all kinds and brands of FPGAs and have been doing so for years and years (the first FPGA I dealt with was a XC2000 under XDE,- 17? years ago-). Until less than two years ago, we did design more Xilinx than Altera parts (we respect the customer's decision when he wants a particular device or family). And ISE is based on a technology (Synario & ECS) that I supported even before it had a name -and I more than liked this tool, still use it occasionnally-. When Quartus was launched, it was terrible, and stayed that way for a while. However... IMO and backed up by concrete experience, I would say that the progress made by Altera with Quartus tools (and devices) over the last two years has been tremendous and probably gone very much unnoticed, until recently. Quartus II has progressed a lot, and it's not over... The new device architectures (like MaxII) are as surprising as they prove efficient concretely. We love the Cyclone family : cheap, extremely low power and they are usually faster than the usual applications require even in their lowest speed grades. - As of tool quality, I keep my fingers crossed, but I don't fear loading the latest QII release (even beta) and start using it right away in the middle of challenging designs. I usually let other tools "ripe" a bit. - As of integrated synthesis, both for QOR and language coverage (VHDL) I won't comment, by fear of offending third party tools vendors. I've witnessed 30% smaller designs with QII v4.2 as compared with older versions, and I have problem with standard descriptions with XST which are perfectly supported by QII now. There are still a few things I would like to see added in QII (like character'pos), but they should be in 5.0 or 5.1 and I stopped asking for VHDL QOR improvement. - QII's Static Timing Analysis + constraint-driven P&R + Physical synthesis are impressive. Most FPGA users need to be educated in order to take advantage of it. Physical synthesis can for example fix design errors by automatically compensating data or clock delays, it can precisely adjust delays for SDRam interfaces, etc... I'm not saying other tools don't have this technology, just that users are often unaware that it's in Quartus II. - Tcl/Tk and command-line tools are so easy to use ! (you find a Tcl console in almost all tools now -yes: ModelSim too : just type parray env-). You can build and download an FPGA with a single double click on a batch file and never see the GUI if you want to, with a trivial script. This contributes greatly to the ease of use of our Tornado FPGA Board and Tornado Education Kit. - SoPC is probably the strongest advantage I see as of now for Altera. The NIOS II processor, the Avalon switch fabric, and the Tools around them have proved their value. I know several companies even purchased the NIOS license... for ASICs. - RTL and Technology graphical Views are very decent, and the cross-probings between all the different descriptions is handy when investigating. - The Constraints Editor, initially clumsy, is now very powerful & versatile. You can for example easily import export CSV pin assignments (with PCB tools or Excell). It is well organized and easy to use. - The GUI commands have their immediately visible Tcl counterpart, so it's a trivial task to automate even the most complex settings. When we deliver an FPGA design to a customer, we only have HDL source files and a single "does-it-all" Tcl script (which also includes the pin & other assignments). - SignalTap and InSystem Memory Contents Editors are _VERY_ easy to use (and cheap if not free). - LogicLock makes floorplanning (almost) easy when the need comes. - JTag (Jam) player is nice in some cases. Not sure Xilinx has the equivalent public code. (well probably) - I think the cost is lower for the full version of QII compared with Foundation and equivalent options (ChipscopePro) but prices move often. - It's very easy to integrate other tools within QII, or to integrate QII inside other tools. I don't think any other tool is as open as QII. - OpenCore IP protection scheme is clever. It lets you play with IPs as you please. The megawizzard is also easy to use. - Power estimation in 4.2 is now simple to use, both as an early tool, then along when the design gets refined. - Early estimators, and fast assignment verifiers, Design assistant, Performance advisors definitely make the designer's life easier. - Never used DSE nor distributed computing (hope I won't have to), but I know it's there. - More new features are announced. As far as I know, Altera bought a couple of small but very brilliant companies that are behind these technology leaps. On the minus side for Altera I would mention : - Truly incremental P&R is coming, but still not quite here yet. Many users are impatient (it will be welcome for the big chips). - For simple designs : Analysis & Elaboration must be run in order to view the hierarchical dependencies (ISE does this automatically), not a real issue but it's a bit unexpected for ISE users when they try QII. For big designs, you don't let the tool guess what it should compile and in which order; we use scripts. It's very easy to use Quartus II and simply not unleash its power even when you need it. That's why we made efforts to build and offer (with lots of help from Altera) an extensive 2-days Training course in France, and we get an excellent feedback on it. What we try to say to our customers is that Quartus II now deserves spending some time learning its many features and capabilities. For simple things, not much if anything at all is necessary (a batch file can do everything), but challenging tasks will be much simpler with a good understanding of the engine under the hood. --- As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback & experience to share ? Obviously, we don't fear designing Xilinx chips (we design mostly very complex applications now) and ISE is easy to use. Besides the lack -as far as I know- of easy and well documented scripting (Tcl/tk), my worst grief is that it's way too easy to have the focus on the wrong design entity :-) This feature didn't exist in Synario, and it was much less error-prone. Definitely minor, but irritating. With QII, you can change your focal point, but you can't do it without noticing. VHDL synthesis (XST) has also some issues and weaknesses, and I sometimes have to partially rewrite some of our IPs for this reason (I complained a couple of times about poor support for qualified expressions for example). I find Impact's look and use a bit clumsy and old-looking, but it works. I guess it has been improved in 7.1. I also hope they removed or rewrote these offending VHDL "examples" !!! (like j2c_vhd on top of my head). On the X. side, I found Xilinx Tech Support outstanding (maybe only ModelSim's does impress me even more). I loved ECS in Synario and first ISE versions, with the generic symbol library and all the cool utilities related with HDL, but I don't like what it became in the latest versions of ISE. But schematic editors are usually a matter of personal taste (I'm not a huge fan of QII's schematic editor either) and we don't use them much if at all (top levels only, if we find enough motivation). If you plan to stay with Xilinx, don't start using Quartus ;-) Things are very cyclic in this industry, so I expect an effort from the competition to regain the lost terrain. It makes things interesting for us to watch. The good news are that the end-user is usually the winner on the end, with powerful and affordable tools and devices. But high-end FPGAs and applications are bringing us lots of challenges : high level descriptions and modelling, ABV, high-speed design, power issues, P&R challenges, IPs reuse, collaborative design... we'll see. Bert Cuzeau --- The opinions above are my own only. --- I may be wrong on some issues. --- If you think so, or believe I am unfair in any way, let me know. Antti Lukats wrote:> Hi > > first - I am a very Xilinx biased (possible because I have way more Xilinx > boards) > but the latest Quartus seems really easy and in some cases better than X > tools > (at least the built in programmer is FASTER to use than impact) > > Story: > After getting a nice application tested on Xilinx FPGA I just out of > curiosity > tried to port to Altera devices, the only problem I had was related to lack > of documentation on the cyclone_jtag and maxii_jtag, after solving those > the original xilinx code compiled without changes and worked too :) > > http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter > > after first success with Cyclone, I tried it on MAX2 and worked again :) > > MAX2 is really nice well its not so much an PLD but more like > Xilinx XC2K reinvented and made flash based ;) anyway it is > really a heavy player on the flash device arena as the other > suppliers Atmel and Lattice are not yet shipping their low-cost > flash FPGAs > > Antti > > > >
Reply by ●March 27, 20052005-03-27
info_ wrote:> [...] > As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback &experience> to share ?There are a few minor improvements here and there (advanced mode is now finally obvious), but save the new design summary screen, the UI for 7.1 appears basicly unchanged from 6.x.> [...] my worst [Xilinx] grief > is that it's way too easy to have the focus on the wrong designentity :-)> This feature didn't exist in Synario, and it was much lesserror-prone.> Definitely minor, but irritating. With QII, you can > change your focal point, but you can't do it without noticing.I've already done that in 7.1.1i, several times. Agreed - quite irritating.> I find Impact's look and use a bit clumsy and old-looking, but itworks.> I guess it has been improved in 7.1. > [...]I haven't used it to program devices directly, only to generate .hex files, it that appears unchanged from 6.x. I agree on your other observations of Impact. It would drive me absolutely crazy if it weren't for .cdf files to save your configuration! Have fun, Marc
Reply by ●March 27, 20052005-03-27
I agree with everything you've said about QII. The last few QII releases have been a joy to use. I upgraded twice in the middle of a major project without regret. SOPC Builder seems to be way ahead of the stuff for Microblaze too. My biggest remaining beef is that GUI-wise LogicLock and tracking down nets in the Timing Floorplanner (forget the real name) is so darn slow, and Phys Synth duplicates nodes it shouldn't have to (although it's a lifesaver if you really need to meet timing). I watched a demo video of PlanAhead for Xilinx which seems to have the same functionality as LogicLock and everything was zipping along at top speed. Maybe they were cheating in the video though. Anyways, eagerly awaiting QII 5.0 now. -- Pete info_ wrote:> Hi Antti, > > At ALSE, we design all kinds and brands of FPGAs and have been doingso for years and> years (the first FPGA I dealt with was a XC2000 under XDE,- 17? yearsago-). Until> less than two years ago, we did design more Xilinx than Altera parts(we respect the> customer's decision when he wants a particular device or family). > And ISE is based on a technology (Synario & ECS) that I supportedeven before it had> a name -and I more than liked this tool, still use it occasionnally-. > When Quartus was launched, it was terrible, and stayed that way for awhile. However...> > IMO and backed up by concrete experience, I would say that theprogress made by> Altera with Quartus tools (and devices) over the last two years hasbeen tremendous> and probably gone very much unnoticed, until recently. > > Quartus II has progressed a lot, and it's not over... > The new device architectures (like MaxII) are as surprising as theyprove efficient> concretely. We love the Cyclone family : cheap, extremely low powerand they are> usually faster than the usual applications require even in theirlowest speed grades.> > - As of tool quality, I keep my fingers crossed, but I don't fearloading the latest> QII release (even beta) and start using it right away in the middleof challenging> designs. I usually let other tools "ripe" a bit. > > - As of integrated synthesis, both for QOR and language coverage(VHDL) I won't> comment, by fear of offending third party tools vendors. I'vewitnessed 30% smaller> designs with QII v4.2 as compared with older versions, and I haveproblem with> standard descriptions with XST which are perfectly supported by QIInow. There are> still a few things I would like to see added in QII (likecharacter'pos), but they> should be in 5.0 or 5.1 and I stopped asking for VHDL QORimprovement.> > - QII's Static Timing Analysis + constraint-driven P&R + Physicalsynthesis are> impressive. Most FPGA users need to be educated in order to takeadvantage of it.> Physical synthesis can for example fix design errors by automaticallycompensating> data or clock delays, it can precisely adjust delays for SDRaminterfaces, etc...> I'm not saying other tools don't have this technology, just thatusers are often> unaware that it's in Quartus II. > > - Tcl/Tk and command-line tools are so easy to use ! (you find a Tclconsole in> almost all tools now -yes: ModelSim too : just type parray env-). > You can build and download an FPGA with a single double click on abatch file and> never see the GUI if you want to, with a trivial script. Thiscontributes greatly to> the ease of use of our Tornado FPGA Board and Tornado Education Kit. > > - SoPC is probably the strongest advantage I see as of now forAltera. The NIOS II> processor, the Avalon switch fabric, and the Tools around them haveproved their> value. I know several companies even purchased the NIOS license...for ASICs.> > - RTL and Technology graphical Views are very decent, and thecross-probings between> all the different descriptions is handy when investigating. > > - The Constraints Editor, initially clumsy, is now very powerful &versatile.> You can for example easily import export CSV pin assignments (withPCB tools or> Excell). It is well organized and easy to use. > > - The GUI commands have their immediately visible Tcl counterpart, soit's a trivial> task to automate even the most complex settings. > When we deliver an FPGA design to a customer, we only have HDL sourcefiles and a> single "does-it-all" Tcl script (which also includes the pin & otherassignments).> > - SignalTap and InSystem Memory Contents Editors are _VERY_ easy touse (and cheap if> not free). > > - LogicLock makes floorplanning (almost) easy when the need comes. > > - JTag (Jam) player is nice in some cases. Not sure Xilinx has theequivalent public> code. (well probably) > > - I think the cost is lower for the full version of QII compared withFoundation and> equivalent options (ChipscopePro) but prices move often. > > - It's very easy to integrate other tools within QII, or to integrateQII inside> other tools. I don't think any other tool is as open as QII. > > - OpenCore IP protection scheme is clever. It lets you play with IPsas you please.> The megawizzard is also easy to use. > > - Power estimation in 4.2 is now simple to use, both as an earlytool, then along> when the design gets refined. > > - Early estimators, and fast assignment verifiers, Design assistant,Performance> advisors definitely make the designer's life easier. > > - Never used DSE nor distributed computing (hope I won't have to),but I know it's there.> > - More new features are announced. > > As far as I know, Altera bought a couple of small but very brilliantcompanies that> are behind these technology leaps. > > On the minus side for Altera I would mention : > - Truly incremental P&R is coming, but still not quite here yet. Manyusers are> impatient (it will be welcome for the big chips). > - For simple designs : Analysis & Elaboration must be run in order toview the> hierarchical dependencies (ISE does this automatically), not a realissue but it's a> bit unexpected for ISE users when they try QII. For big designs, youdon't let the> tool guess what it should compile and in which order; we use scripts. > > It's very easy to use Quartus II and simply not unleash its powereven when you need> it. That's why we made efforts to build and offer (with lots of helpfrom Altera) an> extensive 2-days Training course in France, and we get an excellentfeedback on it.> > What we try to say to our customers is that Quartus II now deservesspending some> time learning its many features and capabilities. For simple things,not much if> anything at all is necessary (a batch file can do everything), butchallenging tasks> will be much simpler with a good understanding of the engine underthe hood.> --- > As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback &experience to share ?> > Obviously, we don't fear designing Xilinx chips (we design mostlyvery complex> applications now) and ISE is easy to use. Besides the lack -as far asI know- of easy> and well documented scripting (Tcl/tk), my worst grief is that it'sway too easy to> have the focus on the wrong design entity :-) This feature didn'texist in Synario,> and it was much less error-prone. Definitely minor, but irritating.With QII, you can> change your focal point, but you can't do it without noticing. > VHDL synthesis (XST) has also some issues and weaknesses, and Isometimes have to> partially rewrite some of our IPs for this reason (I complained acouple of times> about poor support for qualified expressions for example). > I find Impact's look and use a bit clumsy and old-looking, but itworks. I guess it> has been improved in 7.1. > I also hope they removed or rewrote these offending VHDL "examples"!!! (like j2c_vhd> on top of my head). > > On the X. side, I found Xilinx Tech Support outstanding (maybe onlyModelSim's does> impress me even more). > > I loved ECS in Synario and first ISE versions, with the genericsymbol library and> all the cool utilities related with HDL, but I don't like what itbecame in the> latest versions of ISE. But schematic editors are usually a matter ofpersonal taste> (I'm not a huge fan of QII's schematic editor either) and we don'tuse them much if> at all (top levels only, if we find enough motivation). > > If you plan to stay with Xilinx, don't start using Quartus ;-) > > Things are very cyclic in this industry, so I expect an effort fromthe competition> to regain the lost terrain. It makes things interesting for us towatch. The good> news are that the end-user is usually the winner on the end, withpowerful and> affordable tools and devices. But high-end FPGAs and applications arebringing us> lots of challenges : high level descriptions and modelling, ABV,high-speed design,> power issues, P&R challenges, IPs reuse, collaborative design...we'll see.> > > Bert Cuzeau > > --- The opinions above are my own only. > --- I may be wrong on some issues. > --- If you think so, or believe I am unfair in any way, let me know. > > > Antti Lukats wrote: > > Hi > > > > first - I am a very Xilinx biased (possible because I have way moreXilinx> > boards) > > but the latest Quartus seems really easy and in some cases betterthan X> > tools > > (at least the built in programmer is FASTER to use than impact) > > > > Story: > > After getting a nice application tested on Xilinx FPGA I just outof> > curiosity > > tried to port to Altera devices, the only problem I had was relatedto lack> > of documentation on the cyclone_jtag and maxii_jtag, after solvingthose> > the original xilinx code compiled without changes and worked too :) > > > > http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter > > > > after first success with Cyclone, I tried it on MAX2 and workedagain :)> > > > MAX2 is really nice well its not so much an PLD but more like > > Xilinx XC2K reinvented and made flash based ;) anyway it is > > really a heavy player on the flash device arena as the other > > suppliers Atmel and Lattice are not yet shipping their low-cost > > flash FPGAs > > > > Antti > > > > > > > >
Reply by ●March 27, 20052005-03-27
Marc, Thanks a lot for the details ! When productivity is involved, scripting is the way to go, and this gets rid of the GUI irritations. That's why I am more and more sensitive to the scripting offered by tools, and I appreciate when I find extensive Tcl support.
Reply by ●March 29, 20052005-03-29
Antti Lukats wrote:> Hi ><snip>> MAX2 is really nice well its not so much an PLD but more like > Xilinx XC2K reinvented and made flash based ;) anyway it is > really a heavy player on the flash device arena as the other > suppliers Atmel and Lattice are not yet shipping their low-cost > flash FPGAsLattice do have their first LatticeXP devices, but not the smallest ones. Present press releases have their XP10 around $33 in 1K/now, and ~$16 for 250K/2006 prices. No mention of prices on the smallest XP3. Actel claim to have ProASIC3 prices 'from $1.50', but are less clear on specifics.... Have you looked at the ProASIC3 family / tool flows ? -jg
Reply by ●March 29, 20052005-03-29
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:424923d0$1@clear.net.nz...> Antti Lukats wrote: > > > Hi > > > <snip> > > MAX2 is really nice well its not so much an PLD but more like > > Xilinx XC2K reinvented and made flash based ;) anyway it is > > really a heavy player on the flash device arena as the other > > suppliers Atmel and Lattice are not yet shipping their low-cost > > flash FPGAs > > Lattice do have their first LatticeXP devices, but not the > smallest ones. Present press releases have their XP10 > around $33 in 1K/now, and ~$16 for 250K/2006 prices. > No mention of prices on the smallest XP3.And shipping NOW for regular mortals? NO! I guess none of the XP devices are shipping or available.> Actel claim to have ProASIC3 prices 'from $1.50', but are > less clear on specifics....There will be NO ProAsic3 silicon before SEPT 2005 Not even engineering samples. Dont hope.> Have you looked at the ProASIC3 family / tool flows ? > > -jg >Yes I have tried several times. Scary. Sure sometimes the P&R seems to finish succesfully too. I have tried to compile several projects fro ProAsic+ usually yielding in no fit - I only have APA075 eval board and using free license. So far the only succesful use for ProAsic+ has been the Eric5 CPU demo displaying some Hello on LCD Antti
Reply by ●March 29, 20052005-03-29
> Yes I have tried several times. Scary. > Sure sometimes the P&R seems to finish succesfully too. > I have tried to compile several projects fro ProAsic+ > usually yielding in no fit - I only have APA075 eval > board and using free license. > > So far the only succesful use for ProAsic+ has been > the Eric5 CPU demo displaying some Hello on LCD > > Antti >Maybe I should mention that the ProAsic+/3 does not support preinitialized memory-blocks (a pity for a flash-based architecture...), so I had to synthesize the program-ROM into logic-tiles for the ERIC5-demo, which is very space consuming. I managed to use about 73% of the tiles, above that the fitting failed. Regarding MAX II: I am missing memory-blocks (RAM) there... BTW: For "real" Actel-designs with ERIC5, the solution is to bootload the program-memory from an external SPI-flash into the internal memory-blocks, or to use them as cache and execute directly from the SPI-flash. Regards, Thomas www.entner-electronics.com
Reply by ●March 29, 20052005-03-29
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42494101$0$19210$91cee783@newsreader02.highway.telekom.at...> > Yes I have tried several times. Scary. > > Sure sometimes the P&R seems to finish succesfully too. > > I have tried to compile several projects fro ProAsic+ > > usually yielding in no fit - I only have APA075 eval > > board and using free license. > > > > So far the only succesful use for ProAsic+ has been > > the Eric5 CPU demo displaying some Hello on LCD > > > > Antti > > > > Maybe I should mention that the ProAsic+/3 does not support preinitializedyes the init of ProAsic+ and ProAsic3 is a very pity thing :(> memory-blocks (a pity for a flash-based architecture...), so I had to > synthesize the program-ROM into logic-tiles for the ERIC5-demo, which is > very space consuming. I managed to use about 73% of the tiles, above that > the fitting failed.hm then you have seen the same as me, if the utilization goes over 50% chances to get succesful fit get lower and lower, that was the scary thing for me.> Regarding MAX II: I am missing memory-blocks (RAM) there...yes they are missing a register file takes lots of resources. but a small 8 bit SRAM that loads init bootloader from UFM would be nice option for softcore cpu implementation> BTW: For "real" Actel-designs with ERIC5, the solution is to bootload the > program-memory from an external SPI-flash into the internal memory-blocks, > or to use them as cache and execute directly from the SPI-flash. > > Regards, > > Thomas > > www.entner-electronics.com >Hi Thomas you have promised ERIC5 evaluation in MARCH 2005 there isnt much days left if you are about to keep that promise! Antti
Reply by ●March 29, 20052005-03-29
> > Hi Thomas > > you have promised ERIC5 evaluation in MARCH 2005 there isnt much days left > if you are about to keep that promise! > > Antti > >Hey, we are in FPGA business here, you should know marketing ;-) As you say, there are still some days left... In fact I am just working on that eval-stuff. The first download will be for the Nios-Cyclone-Kit, a second is planed for the Spartan-3-Starter-Kit. The hardware will be fixed, but you will be able to write and download your own software onto the board. There will be no eval-download for Actel, as the ProAsicPlus-Kit has no RS-232 (I do not think that people will start soldering a RS-232-adapter, just to test-drive ERIC5). Regards, Thomas www.entner-electronics.com P.S.: Of course, I'll try to keep my promise!