RAMB16_S9

Hi,

I am trying to use RAMB16_S9 to store some data. Since this is my first time doing this, I am trying to test it to see how it works. I let wr_en = 1 for 256 cycle, and make wr_en = 0 for 256 clk cycle. But I am running into problem. It looks like the data never got written in or something. The data coming out is always 00000000. Can someone help? Thanks. This is what my code look like:

main module: counter mycounter (.clk(FPGA_CLK), .write_en(wr_en), .reset(1'b0));

RAMB16_S9 top_ram (.DO(user_DO), .ADDR(11'b00000001000), .CLK(FPGA_CLK), .DI(8'b00001000), .EN(1'b1), .SSR(1'b0), .WE(wr_en), .DIP(DIP), .DOP(DOP));

Counter module: parameter 	IDLE = 0, 	WRITE = 1, 	READ = 2, 	DONE = 3; always @(posedge clk) begin 	if (reset) 	begin 		count <= 0; 		write_en <= 1'b0; 		state <= IDLE; 	end 	else 	begin 	case (state) 	IDLE: 	begin 		count <= 0; 		write_en <= 1'b0; 		state <= WRITE; 	end 	WRITE: 	begin 	if (count < 255) 	begin 	 count	<= count + 1; 	 write_en <= 1'b1; 	end	 	else 	begin 	 count <= 0; 	 state <= READ; 	end 	end 	READ: 	begin 	if (count < 255) 	begin 	 count <= count + 1; 	 write_en <= 1'b0; 	end 	else 	begin 	 count <= 255; 	 state <= DONE; 	end 	end 	DONE: 	begin 	 state <= DONE; 	end 	default: state <= IDLE; 	endcase 	end end

Try this link

http://ece.gmu.edu/courses/ECE449/viewgraphs_S05/449_lecture3.html

It has some information about how to use the memory. Although it is not
in verilog (the course is about VHDL), it should be helpful. 

Milind

Hi, I have read these materials before I wrote the code, and I have just re-read it, seems like the way that I instantiate the code is write. I don't know why the data is not there though. Does anyone have an example or something? Thanks, Ann

"Ann" <ann.lai@analog.com> wrote in message news:ee8d229.1@webx.sUN8CHnE...
> Hi, I have read these materials before I wrote the code, and I have just
re-read it, seems like the way that I instantiate the code is write. I don't
know why the data is not there though. Does anyone have an example or
something? Thanks, Ann

I looked at your code segments earlier and it looks 100% correct.  The state
machine goes through 256 writes to the same address.  The first write to
that address should produce a valid read value.  As long as your clock is
verifiably there, I'd suggest you could have a mistake in the code that
reports the read value *suggesting* that the read value is zero when it
isn't.

I hope you find the trouble.

- John_H
(by the way, your posts aren't wrapping when sent causing some problems in
other newsreaders)

Hi, for some reason, the write line have to toggle high and low for me to write and read data back. I thought for this kind of memory module, you only need WE to be high to write, and WE to be low when you read. If in my state machine, I have 10 write cycle where I set WE <= 1'b1, then the rest read and keep looping in read where I set WE = 1'b0, it doesn't work. If I set it to write 10 cycles, read 10 cycles, write 10 cycles, read 10 cycles...etc, then it works. Does anyone know what is wrong? I am terribly confused. Thanks, Ann

If you're simulating, look for the wr_en being assigned 0 outside the always
block you showed us; this would present odd behavior.

The Block RAM absolutely does not require the WE edge.  The WE level is
sampled on the rising edge of the clock to the BlockRAM with specific setup
and hold requirements.

Are you simulating, using ChipScope, looking at test points, or other?

"Ann" <ann.lai@analog.com> wrote in message news:ee8d229.3@webx.sUN8CHnE...
> Hi, for some reason, the write line have to toggle high and low for me to
write and read data back. I thought for this kind of memory module, you only
need WE to be high to write, and WE to be low when you read. If in my state
machine, I have 10 write cycle where I set WE <= 1'b1, then the rest read
and keep looping in read where I set WE = 1'b0, it doesn't work. If I set it
to write 10 cycles, read 10 cycles, write 10 cycles, read 10 cycles...etc,
then it works. Does anyone know what is wrong? I am terribly confused.
Thanks, Ann

Hi, I am simulating using ModelSim. I saw that WE do get "0" and the address coming in is changing, but still data out is always 0 for some reason :-\ Thanks, Ann

Make sure you are correctly using glbl.v:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6537

This is sometimes tricky to get right because of the various timescale
in each module.  However, look at the waveforms and make sure that you
wait long enough for glbl.GSR to go low so the BRAM output registers
actually pass the data out of the module. 

Paul

Ann wrote:
> 
> Hi, I am simulating using ModelSim. I saw that WE do get "0" and the address coming in is changing, but still data out is always 0 for some reason :-\ Thanks, Ann

Hi, It works now. But for some reason, the data read out is one cycle late. Is this how it supposed to be. For example, I set it up so that it store value 0 at address 0, 1 at address 1, 2 at 2, 3 at 3 etc. But when I read back, address 1 read back 0, address 2 read back 1, address 3 read back 2, etc. Thanks, Ann

Keep in mind that the write data goes to the write address at the sampling
clock edge.
Read data comes from the read address sampled on the clock edge becoming
valid a few nanoseconds later.
If you're looking at what the address is in your simulation when you look at
the data that's coming back from the BlockRAM, they will be one cycle skewed
because the address you see is the address for the read data AFTER the clock
edge.

These memories are synchronous.
Look at the Xilinx page on the primitive -
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/lib/lib0346_332.html -
and you'll see the logic table for the BlockRAM.  Note that there are three
different modes for reading and writing at the same time for this single
port memory set by a parameter.  The RAMB16_S9_S9 is a dual-port memory that
allows independent read and write addresses to the same memory array.


"Ann" <ann.lai@analog.com> wrote in message news:ee8d229.7@webx.sUN8CHnE...
> Hi, It works now. But for some reason, the data read out is one cycle
late. Is this how it supposed to be. For example, I set it up so that it
store value 0 at address 0, 1 at address 1, 2 at 2, 3 at 3 etc. But when I
read back, address 1 read back 0, address 2 read back 1, address 3 read back
2, etc. Thanks, Ann