RAMB16_S9

For some reason, this only works in simulation, when I probe the pins on the chip, nothing shows up. If i have the WE toggle, then it works, I can see the data whenever WE is low. If after setting WE to 1'b1 for 20 cycles, I set WE to low all the time, no data on the scope. I triggered on the negative edge WE on the Oscilloscope and WE looks like it went to 1.2 V so not quiet a "1" and data[0] went to like 1.02 and that's it, nothing else happens. Same thing happens when I trigger on the rising edge of data[0].

If your probes show that electrically the signals are not what you expect in
a digital signal, the power supplies to your chip may be wrong.  Please
check your device for appropriate voltages to Vcco, Vccaux, and Vccint
relative to ground.  Have you verified that the chip is programming
correctly?  Are you driving an unusual load such as a 30 ohm resistor?  Do
you have your I/O signal format specified in your constraints as LVCMOS?
LVTTL?  2mA?  24ma?  What frequency is the design running?

If the rest checks out, bottom line is if the I/O are bad, the design will
run bad.  A transition on WE may give the signal enough "oomph" to get past
the invalid logic level to something that registers.

With 1.2V and 1.02V signals, something is very wrong.  It's certainly not
the RAMB16_S9 primitive that's having troubles.


"Ann" <ann.lai@analog.com> wrote in message news:ee8d229.9@webx.sUN8CHnE...
> For some reason, this only works in simulation, when I probe the pins on
the chip, nothing shows up. If i have the WE toggle, then it works, I can
see the data whenever WE is low. If after setting WE to 1'b1 for 20 cycles,
I set WE to low all the time, no data on the scope. I triggered on the
negative edge WE on the Oscilloscope and WE looks like it went to 1.2 V so
not quiet a "1" and data[0] went to like 1.02 and that's it, nothing else
happens. Same thing happens when I trigger on the rising edge of data[0].

Hi, I have checked, Vcco, Vccaux, and Vccint are correct, other designs work fine. The input clk is 30 MHz and I have used this frequency before for all my other designs, and the chip can handle it. But the question is how come it works right when I toggle the WE signal. It works exactly like how you would expected it to. It's only when I have WE high for write then 0 the rest of the way, then it's didn't behave like the ModelSim Simulation, I am really confused!!! In my ucf file I didn't add any constraint to the signal. I don't see a reason to, but should I? Thanks, Ann

The reason the problems exist is that your I/O isn't valid.
Bottom line, if you have bad input, you'll probably get bad output.

If your write enable has some "reason" to be 1.2V logic high for LVCMOS33,
toggling the signal low then high will present a higher voltage until the
signal again reaches a DC level of 1.2V.  You get a valid state for a short
amount of time before you get an invalid.

Show me why the I/O are not giving valid digital levels and you'll find why
your design isn't "working."


"Ann" <ann.lai@analog.com> wrote in message news:ee8d229.11@webx.sUN8CHnE...
> Hi, I have checked, Vcco, Vccaux, and Vccint are correct, other designs
work fine. The input clk is 30 MHz and I have used this frequency before for
all my other designs, and the chip can handle it. But the question is how
come it works right when I toggle the WE signal. It works exactly like how
you would expected it to. It's only when I have WE high for write then 0 the
rest of the way, then it's didn't behave like the ModelSim Simulation, I am
really confused!!! In my ucf file I didn't add any constraint to the signal.
I don't see a reason to, but should I? Thanks, Ann