Reverse engineering ASIC into FPGA

Does anyone have experience with reverse engineering ASIC (black box)
into equivelant FPGA devices (pin equivelant with a sub-board if necessary)?


-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Yes.
"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message 
news:slrnd52ogp.ivg.weingart@irricana.cs.ualberta.ca...
> Does anyone have experience with reverse engineering ASIC (black box)
> into equivelant FPGA devices (pin equivelant with a sub-board if 
> necessary)?
>

On Mon, 4 Apr 2005 10:12:21 -0700, "Symon" <symon_brewer@hotmail.com>
wrote:

>Yes.
>"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message 
>news:slrnd52ogp.ivg.weingart@irricana.cs.ualberta.ca...
>> Does anyone have experience with reverse engineering ASIC (black box)
>> into equivelant FPGA devices (pin equivelant with a sub-board if 
>> necessary)?
>>
>

you mean you decapped a chip, looked at the layout with a microscope,
re-drew the polygons and generated a flat gate-level netlist ? ;-)

"mk" <kal*@dspia.*comdelete> wrote in message 
news:btt251hsfuth938fd2amhv0njtrmeem9ob@4ax.com...
> On Mon, 4 Apr 2005 10:12:21 -0700, "Symon" <symon_brewer@hotmail.com>
> wrote:
>
> you mean you decapped a chip, looked at the layout with a microscope,
> re-drew the polygons and generated a flat gate-level netlist ? ;-)
>
Naahh, I sent a copy of the databook to Pune, India. Three months later, 
during which time we had a board relayout with a bigger FPGA, I got the VHDL 
back along with a bloke from India. He stuck the VHDL into the FPGA and 
debugged it. We sent them money. Easy as that, I even got to spend some time 
in Bangalore and Goa 'researching' the best VHDL houses!
Cheers, Syms. 

mmm, next time you want one done send me to India ! Haven't been there yet
:)

Depends how big the asic is and how much info you have on it.

www.fpgaarcade.com

I have cloned a few early NAMCO asics and made plug in 28pin replacements.
No documentation on them, but functionally simple. Very small amounts of
code compared to my normal large virtex4 type stuff, but lots of debugging
and trial and error to get exact behaviour under all (tested at least)
cases.

I have also (almost) finished the atari st custom chip sets, for which there
is a lot of documentation.

What are you after ?
/Mike.

oh, I also have written a number of tools to turn various asic netlists back
into VHDL  ...
Again, all depends what you want to do.

currently we are doing one such assignemnt for a client. They want to
do a board respin and wanted us to replace the few asics in there with
fpga's. but fortunately they are not complex but the process sucks.
less or no documentation or its in some foreign language, crazy!! and
nothing for reference except the working board. so its like code,
debug,debug,debug...until you get it right on the screen.

"Neo" <zingafriend@yahoo.com> wrote in message 
news:1112686978.009999.201120@g14g2000cwa.googlegroups.com...
> currently we are doing one such assignemnt for a client. They want to
> do a board respin and wanted us to replace the few asics in there with
> fpga's. but fortunately they are not complex but the process sucks.
> less or no documentation or its in some foreign language, crazy!! and
> nothing for reference except the working board. so its like code,
> debug,debug,debug...until you get it right on the screen.
>
How do you go about quoting that, or is it by the hour?

If it's by the hour, how do you even give a vague estimate? 

At one time I worked for a company that did chip IP reverse engineering
usually by the stitched photo capture route, long before India was
doing anything in that area and also long before FPGAs could host
anything but glue logic.

Such projects used to be billed for many 100Ks or low $mil or so, after
all its incredibly labour intensive typically had half a dozen sets of
eyeballs categorizing stitched plots and then figuring what the netlist
was from that.  Atleast one contractor actually did lose his marbles
and was later found by police doing some strange things....

It can be automated to some extent but that requires the scanned images
to be "corrected" before tiling. And getting EBES pics didn't seem to
work out too well either. We just used robo step & repeat high end
micro photography and sweat & tears.

Much more fun when it was transister level since you never quite knew
what sort of circuit structure would pop up and that needed EEs rather
than technician level to put a netlist together that made any sense but
the flip side was that hand layed out chips are easier for humans to
figure out too if you think the same way. The huge std cell arrays
though have no logical structure to guide, all random placed so nothing
much to infer.

We even had a nice little DSP project from a former great company that
had to reverse engineer its own chip since maybe 15yrs had passed and
that was many technology generations old back to nmos days but they did
give masks and vecs, just no netlist.

Usually the customer for such services never sees any of the results,
not even the netlist. They forward design their own clean room
compatible design as best they can from open docs but when they need to
know what the chip is supposed to do with a set of vectors, they'd get
our guys to run same vecs on extracted netlist on some HW simulator.

And only the really big companies could afford that sort of service but
had to have legally safe way of checking their own designs. Usually
getting a license from a competitor was unacceptable to them so they
dig in an clone the part.

regards

johnjakson at usa dot com

All,

I know that we have customers who have ASICs on obsolete process nodes, 
which can not be ecconmically obtained.

We have exactly the same problem, as is evidenced by our phasing out of 
the XC2000, and the XC3000 (although we still supply the XC3100A in some 
packages and parts for a while yet).

In fact, I talked with one company that converts about 50 ASICs a year 
into our FPGAs, because they can't fabricate these old ASICs any longer.

One big advantage they have, is they have schematics, verilog, or VHDL, 
so they can simulate, and put together test benches.

Without the schematics, or HDL, it is a very tough job to convert to 
anything at all.

Austin