"Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote in message news:4252c3dc$0$3114$8fcfb975@news.wanadoo.fr...> Hi, > > Are ISA covered by patents or trademarks? Is it allowed to develop a > processor core for a popular ISA as long as no reference is made to any of > the original company trademarks? Many thanks for your comments. >Trademarks cover only product *names*. ISA names can indeed be trademarked, hower that would not prevent anyone from copying/using the architecture. It would only prevent them from selling/promoting/advertising it under the same name as the original. dk
ISA vs. patent/trademark
Started by ●April 5, 2005
Reply by ●April 6, 20052005-04-06
Reply by ●April 6, 20052005-04-06
In comp.arch larwe@larwe.com wrote:> > > > Are ISA covered by patents or trademarks? Is it allowed to develop a > > processor core for a popular ISA as long as no reference is made to > any > > Depends on the ISA. ARM, for instance, is covered by thick IP > protection layers, and is vigorously defended. 8051, not so much :) >Are you sure? A lot of the layers appear to be camoflage and not actual protection. The ARM business case appears to be: 1) milk money from people who buy ARM IP 2) if you see somebody else making ARMs, sue 3) try to get an out of court settlement at all costs 4) including by paying the "offender" lots of cash to go away, stop making ARMs and being quiet about the whole business -- Sander +++ Out of cheese error +++
Reply by ●April 6, 20052005-04-06
"JJ" <johnjakson@yahoo.com> skrev i meddelandet news:1112742200.599044.301840@g14g2000cwa.googlegroups.com...> Q > If some processor that is not any way MIPs like can otherwise perform a > register ld/st for a word on any byte boundary is that a problem, or > only if the rest of it is MIPs like too. > > > If a processor has a general move n bytes ie mv rd,rs,4 and works on > any boundary and any length into memory locations that are also a > register, a problem?. > > Am I not mistaken that most all cpus allowed unaligned ld/st till the > RISC religion took over. Guess I will have to look at the patent. > > johnjakson at usa dot com >The Series 32000 definitely had that capability and that was available already in 1982. This was a microcoded machine, but I do not know if the unaligned functions was implemented in microcode. All machines had 32 bit datapaths and registers, and the NS32032 had a 32 bit bus already in 1985. Dont know the background of the invention. In 1985 there was It is very hard to invent new things -- Best Regards Ulf Samuelsson ulf@atmel.com Atmel Nordic AB Mail: Box 2033, 174 02 Sundbyberg, Sweden Visit: Kavalleriv�gen 24, 174 58 Sundbyberg, Sweden Phone +46 (8) 441 54 22 Fax +46 (8) 441 54 29 GSM +46 (706) 22 44 57 Technical support when I am not available: AT89 C51 Applications Group: mailto:micro@nto.atmel.com AT90 AVR Applications Group: mailto:avr@atmel.com AT91 ARM Applications Group: mailto:at91support@atmel.com FPSLIC Application Group: mailto:fpslic@atmel.com Best AVR link: www.avrfreaks.net
Reply by ●April 6, 20052005-04-06
Dan Koren wrote:> "Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote in message > news:4252c3dc$0$3114$8fcfb975@news.wanadoo.fr... > >>Hi, >> >>Are ISA covered by patents or trademarks? Is it allowed to develop a >>processor core for a popular ISA as long as no reference is made to any of >>the original company trademarks? Many thanks for your comments. >> > > > > Trademarks cover only product *names*. > > ISA names can indeed be trademarked, > hower that would not prevent anyone > from copying/using the architecture. > > It would only prevent them from > selling/promoting/advertising it > under the same name as the original. >There is a case of this years ago: The Zilog Z80 used the Intel 8080/8085 instruction set and extended it, but used different mnemonics for nearly all instructions. -- Tauno Voipio tauno voipio (at) iki fi'
Reply by ●April 6, 20052005-04-06
On Wed, 06 Apr 2005 11:08:53 +1200, Jim Granville wrote:> > I heard that the NIOS II is 'very similar' to MIPS - can anyone who > knows both cores in detail comment ? > > -jgI don't know the MIPS in detail (long ago, I read a book on the R2000/R3000 architecture which I picked up in a second-hand bookshop), but there are certainly some fundamental similarities. Each is a 32-bit RISC core, with 32x32-bit registers, orthogonal instruction set, etc. The NIOS II is a little odd (IMHO) in that it has some registers with dedicated purposes and supervisor-only access. I think, however, that quite a lot of 32-bit RISC architectures (ARM, Microblaize) would be "very similar" at this level. The Nios I was a very different beast, and used sliding register windows in the manner of Sparc. Perhaps the comment you heard was more on the lines of "The NIOS II, unlike the original NIOS, is more of a standard RISC core, such as MIPS" ? mvh., David
Reply by ●April 6, 20052005-04-06
"Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes:> > The basis of the patent is the "ARM Ltd discovery" that less code is better > than more code. > Code compression for RISC is mentioned already in the original RISC paper by > Katevenis.Original RISC paper by Katevenis? While I was able to find a 1983 paper by him, near as I can tell the original RISC paper is still the one by Patterson amd Ditzel in 1980. -- Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605 Department of Computer Science FAX -- (505) 646-1002 New Mexico State University http://www.cs.nmsu.edu/~pfeiffer
Reply by ●April 6, 20052005-04-06
> > That hasn't stopped people from implementing processors with the MIPS > > ISA, *except* for the patented instructions. But the people doing > > this are very careful about not calling the processor for anything > > related to MIPS... > > I heard that the NIOS II is 'very similar' to MIPS - can anyone who > knows both cores in detail comment ?It's (NIOS II) a 32-bit, 32 register RISC, but.. Different exception mechanism, different way of doing multiplies (no special registers), smaller instruction set, no branch delay slots, no unaligned load/stores, no fpu, no load-locked/store-conditional, no coprocessors, no 16-bit isa. So not really. Cheers, Jon
Reply by ●April 6, 20052005-04-06
In article <1bhdikbazp.fsf@cs.nmsu.edu>, Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: |> "Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes: |> > |> > The basis of the patent is the "ARM Ltd discovery" that less code is better |> > than more code. |> > Code compression for RISC is mentioned already in the original RISC paper by |> > Katevenis. |> |> Original RISC paper by Katevenis? While I was able to find a 1983 |> paper by him, near as I can tell the original RISC paper is still the |> one by Patterson amd Ditzel in 1980. There were papers containing much of the technical content in the 1960s. Regards, Nick Maclaren.
Reply by ●April 6, 20052005-04-06
Ulf Samuelsson <ulf@NOSPAMatmel.com> wrote: +--------------- | I happen to think that the ARM Thumb patent is a load of rubbish. +--------------- Yup. See my previous posting about the LINC/LINC-8/PDP-12 machines... -Rob ----- Rob Warnock <rpw3@rpw3.org> 627 26th Avenue <URL:http://rpw3.org/> San Mateo, CA 94403 (650)572-2607
Reply by ●April 6, 20052005-04-06
nmm1@cus.cam.ac.uk (Nick Maclaren) writes:> In article <1bhdikbazp.fsf@cs.nmsu.edu>, > Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: > |> "Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes: > |> > > |> > The basis of the patent is the "ARM Ltd discovery" that less code is better > |> > than more code. > |> > Code compression for RISC is mentioned already in the original RISC paper by > |> > Katevenis. > |> > |> Original RISC paper by Katevenis? While I was able to find a 1983 > |> paper by him, near as I can tell the original RISC paper is still the > |> one by Patterson amd Ditzel in 1980. > > There were papers containing much of the technical content in the > 1960s.Of course. But the one that tied it all together in a single, coherent bundle was Patterson and Ditzel. -- Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605 Department of Computer Science FAX -- (505) 646-1002 New Mexico State University http://www.cs.nmsu.edu/~pfeiffer
