ISA vs. patent/trademark

On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio
<tauno.voipio@iki.fi.NOSPAM.invalid> wrote:

[...]
>
>There is a case of this years ago: The Zilog Z80
>used the Intel 8080/8085 instruction set and extended
>it, but used different mnemonics for nearly all
>instructions.

Similar case with the NEC V20/Intel 8088

Regards,

                               -=Dave
-- 
Change is inevitable, progress is not.

Ulf Samuelsson wrote:

> You protect an ISA by patenting some special thing which is required
to
> implement the ISA.
> I happen to think that the ARM Thumb patent is a load of rubbish.

> The basis of the patent is the "ARM Ltd discovery" that less code is
better
> than more code.
> Code compression for RISC is mentioned already in the original RISC
paper by
> Katevenis.

I note that the Itanium ISA is covered by a patent on its unique method
of explicitly indicating parallelism. The more conventional way of
indicating parallelism, by a 'parallel' bit on each instruction, was
used on TI signal processing chips.

I'm sad to hear that there is a patent on the ARM Thumb instruction set
that extends to the general principle, because something like it is
what the PowerPC architecture desperately needs - so that people can
use it the way IBM wants, without compromising the architecture.

John Savard

Tauno Voipio wrote:

> There is a case of this years ago: The Zilog Z80
> used the Intel 8080/8085 instruction set and extended
> it, but used different mnemonics for nearly all
> instructions.

Note that this was because Intel *copyrighted* the mnemonics, rather
than trademarking them, however.

John Savard

Dave Hansen wrote:
> On Wed, 06 Apr 2005 06:21:44 GMT, Tauno Voipio
> <tauno.voipio@iki.fi.NOSPAM.invalid> wrote:
> 
> [...]
> 
>>There is a case of this years ago: The Zilog Z80
>>used the Intel 8080/8085 instruction set and extended
>>it, but used different mnemonics for nearly all
>>instructions.
> 
> 
> Similar case with the NEC V20/Intel 8088
> 

Yep - the V20 contained the 8080 instruction set as well.

I wrote a CP/M handler running on a PC/XT with V20.

-- 

Tauno Voipio
tauno voipio (at) iki fi

Tauno Voipio <tauno.voipio@iki.fi.NOSPAM.invalid> writes:
> Dan Koren wrote:
> > "Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote
> >>
> >>Are ISA covered by patents or trademarks? Is it allowed to develop a 
> >>processor core for a popular ISA as long as no reference is made to any of 
> >>the original company trademarks? Many thanks for your comments.
> > 
> > Trademarks cover only product *names*.
> > 
> > ISA names can indeed be trademarked,
> > hower that would not prevent anyone
> > from copying/using the architecture.
> > 
> > It would only prevent them from
> > selling/promoting/advertising it
> > under the same name as the original.
> 
> There is a case of this years ago: The Zilog Z80
> used the Intel 8080/8085 instruction set and extended
> it, but used different mnemonics for nearly all
> instructions.

It always puzzled me as to how Intel could get a copyright
on instruction mnemonics.  This struck me as being akin to
someone copyrighting the Latin alphabet.  An AND, is an
AND, is an AND,...

"JJ" <johnjakson@yahoo.com> writes:
> If some processor that is not any way MIPs like can otherwise perform a
> register ld/st for a word on any byte boundary is that a problem, or
> only if the rest of it is MIPs like too.

It's not the unaligned load/store per se that is patented; many processors
have done that.

What MIPS invented and patented was the idea that instead of having the
hardware deal with unaligned bus accesses, they require software to
issue *two* instructions to do an unaligned access.  One does the
"left part" and one does the "right part" of the word.

The normal MIPS load and store instructions require alignment just as
on most other RISC processors.

Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
> Of course.  But the one that tied it all together in a single,
> coherent bundle was Patterson and Ditzel.

Are you asserting that the IBM 801 papers didn't tie it all together
in a single coherent bundle?

mojaveg@mojaveg.iwvisp.com (Everett M. Greene) writes:
> It always puzzled me as to how Intel could get a copyright
> on instruction mnemonics.  This struck me as being akin to
> someone copyrighting the Latin alphabet.  An AND, is an
> AND, is an AND,...

AFAIK the validity of the copyright on the mnemonics was never tested in
court.  It seems unlikely that it would be upheld.

Eric Smith <eric@brouhaha.com> writes:

> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
> > Of course.  But the one that tied it all together in a single,
> > coherent bundle was Patterson and Ditzel.
> 
> Are you asserting that the IBM 801 papers didn't tie it all together
> in a single coherent bundle?

The earliest 801 paper I'm familiar with was published in 1982.  While
the project certainly tied things together in a coherent RISC bundle
before the RISC and MIPS projects (as both Hennessy and Patterson
acknowledge),  Patterson and Ditzel is the first publication I'm aware
of that does.
-- 
Joseph J. Pfeiffer, Jr., Ph.D.       Phone -- (505) 646-1605
Department of Computer Science       FAX   -- (505) 646-1002
New Mexico State University          http://www.cs.nmsu.edu/~pfeiffer

Thanks for clarification, thats okay then!

Perhaps it worth inventing/patenting same idea for exactly 3 & 4 & 5
instructions too:-)

johnjakson at usa dot com
transputer2 at yahoo dot com