Xilinx ISE 7.1i / stuck down XCR3064 outputs

Hi,

I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064.
What seemed to happen was any pin configured as an output was stuck
down to ground (able to draw 30mA) This happens even if the pins are
internally connected (thru an obuf) to VCC or set to 1 in the design.
Pins configured as input seems to work correctly.. high impedance and
doing a sort of a floating latch behavior.

I assumed the chip was blown (dead bug wired VQ44), and get a Digilent
XCR demo board.  Works great with the program it came with, no go with
anything I try to create.  I load the JEDEC I extracted from it, back
into it by way of Impact... works fine.

Their example code (xcrdemo.vhd and xcrdemo.ucf from
https://www.digilentinc.com/Data/Products/DXCR/DXCR-demo.zip)  compiles
and fits fine, programs and verifies fine, but no lights/doesn't work!

Their example code compiles and fits fine on a Windows machine with
ISE4.2WPO.  I take the JEDEC file created on the 4.2 machine back to
Impact on the Linux/ISE7.1 machine, and I've got lights again.

If I take the .ngd file from 7.1 Linux and try to generate a .jed file
on the 4.2 Windows, I get weird "can't read memory" errors.

If I take the .ngd file from 4.2 Windows and generate a .jed file on
the Linux machine, it seems fine, but NO LIGHTS!

This ISE 7.1/Linux machine generates working .bit files for a XC2S200E
FPGA.

Thanks for any help,

Alex

alex at dee en el en kay dot com

"Alex" <alex@dnlnk.com> wrote in message
news:1112826095.036718.103170@l41g2000cwc.googlegroups.com...
> Hi,
>
> I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064.
> What seemed to happen was any pin configured as an output was stuck
> down to ground (able to draw 30mA) This happens even if the pins are
> internally connected (thru an obuf) to VCC or set to 1 in the design.
> Pins configured as input seems to work correctly.. high impedance and
> doing a sort of a floating latch behavior.
>
> I assumed the chip was blown (dead bug wired VQ44), and get a Digilent
> XCR demo board.  Works great with the program it came with, no go with
> anything I try to create.  I load the JEDEC I extracted from it, back
> into it by way of Impact... works fine.
>
> Their example code (xcrdemo.vhd and xcrdemo.ucf from
> https://www.digilentinc.com/Data/Products/DXCR/DXCR-demo.zip)  compiles
> and fits fine, programs and verifies fine, but no lights/doesn't work!
>
> Their example code compiles and fits fine on a Windows machine with
> ISE4.2WPO.  I take the JEDEC file created on the 4.2 machine back to
> Impact on the Linux/ISE7.1 machine, and I've got lights again.
>
> If I take the .ngd file from 7.1 Linux and try to generate a .jed file
> on the 4.2 Windows, I get weird "can't read memory" errors.
>
> If I take the .ngd file from 4.2 Windows and generate a .jed file on
> the Linux machine, it seems fine, but NO LIGHTS!
>
> This ISE 7.1/Linux machine generates working .bit files for a XC2S200E
> FPGA.
>
> Thanks for any help,
>
> Alex
>
> alex at dee en el en kay dot com
>

I have a problem where ISE 7.1.01i inverts all the outputs on my XC95108. I
opened a web case and Xilinx said that it was an issue with the jedec
generation and to go back to ISE 6.3.

Ross

Thanks...
Wow.  I hope they make a fix availiable.  Can anyone point me to a way
to easily run a working fitter from linux?

I tried out their "webfitter"  It works.. it even makes my design work.
 But I need more control over the software if I'm going to bet my
design future on their parts.

Alex

Alex wrote:
> Thanks...
> Wow.  I hope they make a fix availiable.  Can anyone point me to a way
> to easily run a working fitter from linux?
> 
> I tried out their "webfitter"  It works.. it even makes my design work.
>  But I need more control over the software if I'm going to bet my
> design future on their parts.

  These 'school boy' issues with the more mature CPLDs certainly makes 
their testing program look thin/non-existant.
  Perhaps it is all a ploy to move designs to the latest "hot new
thing" - or maybe they have too many ex-microsoft employees ?:)

-jg

Are there non-Xilinx, "zero" static power CPLD options which are
targetable from tools that'll run under Linux?

Alex

"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:4254b2ad@clear.net.nz...
> Alex wrote:
>  These 'school boy' issues with the more mature CPLDs certainly makes 
> their testing program look thin/non-existant.
>  Perhaps it is all a ploy to move designs to the latest "hot new
> thing" - or maybe they have too many ex-microsoft employees ?:)

Jim,
Indeed. You'd think they'd have a bunch of hardware with all these parts on 
them and run a regression test with new releases. As in earlier an earlier 
thread, I'll be waiting a service pack or three before swapping!
Cheers, Syms. 

This appears to be fixed in 7.1i the patch from this page:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21168


WebPACK is a free downloadable ISE subset that now supports Linux.
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=DS-ISE-WEBPACK

Regards,
Arthur