Hello, I am designing a system using Virtex 4 FPGA. The FPGA is interfaced with a 12-bit A/D. The problem is that the A/D generates an inherent dc component in the digital values it ships to the FPGA. This is impacting my results at the lower end of my specs. The methods I have thought of are 1. Trim the A/D manually using a resistor 2. pass the lower 3-bits of the A/D word through a large moving average filter at the input(filter design is a pain!!) Is there any other method which can be used Thanks MORPHEUS
DC component removal in FPGA
Started by ●April 11, 2005
Reply by ●April 11, 20052005-04-11
"morpheus" <saurster@gmail.com> schrieb im Newsbeitrag news:1113232619.700616.34200@z14g2000cwz.googlegroups.com...> Hello, > I am designing a system using Virtex 4 FPGA. The FPGA is interfaced > with a 12-bit A/D. The problem is that the A/D generates an inherent dc > component in the digital values it ships to the FPGA. This is impacting > my results at the lower end of my specs. > The methods I have thought of are > 1. Trim the A/D manually using a resistor > 2. pass the lower 3-bits of the A/D word through a large moving average > filter at the input(filter design is a pain!!) > Is there any other method which can be used > Thanks > MORPHEUS >Check out Ken Chapmans TechExclusives at www.xilinx.com there its explained how todo this antti http://gforge.openchip.org
Reply by ●April 11, 20052005-04-11
morpheus wrote:>Hello, >I am designing a system using Virtex 4 FPGA. The FPGA is interfaced >with a 12-bit A/D. The problem is that the A/D generates an inherent dc >component in the digital values it ships to the FPGA. This is impacting >my results at the lower end of my specs. >The methods I have thought of are >1. Trim the A/D manually using a resistor >2. pass the lower 3-bits of the A/D word through a large moving average >filter at the input(filter design is a pain!!) >Is there any other method which can be used >Thanks >MORPHEUS > > >If you can afford run a calibrate cycle at start-up, you can subtract the DC using a simple adder in the FPGA. Finding the value to subtract (and adjusting it as the DC offset drifts) is the hard part. You can use a CIC filter with a fairly high decimation ratio to extract the DC value with relatively little complexity. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●April 11, 20052005-04-11
On 11 Apr 2005 08:16:59 -0700, "morpheus" <saurster@gmail.com> wrote:>Hello, >I am designing a system using Virtex 4 FPGA. The FPGA is interfaced >with a 12-bit A/D. The problem is that the A/D generates an inherent dc >component in the digital values it ships to the FPGA. This is impacting >my results at the lower end of my specs. >The methods I have thought of are >1. Trim the A/D manually using a resistor >2. pass the lower 3-bits of the A/D word through a large moving average >filter at the input(filter design is a pain!!) >Is there any other method which can be used >Thanks >MORPHEUSExponentially smooth the incoming samples to get the average value, and subtract that from the data stream. Kohn
Reply by ●April 11, 20052005-04-11
Reply by ●April 12, 20052005-04-12
On 11 Apr 2005 19:44:28 -0700, "morpheus" <saurster@gmail.com> wrote:>Kohn, >Thanks for replying, could you elaborate a little more >Thanks >MORPHEUSExponential smoothing just simulates an R-C lowpass filter. Define a filter box, with samples S coming in and output F going out. Now, every sample clock, do F = F + (S-F) / N where N is the smoothing factor. If N is a power of two, the divide is just a right-shift. So you can do this with just a register, two adders, and a misaligned bus to do the shift. F will settle to the mean value of S. Keep N pretty big to reduce the small output ripple, or cascade two filter boxes. Making the filter word size bigger than the ADC "S" word width helps a bit; in other words, keep some or at least a few bits of the right-shifted stuff. So just subtract F from each incoming sample. (S-F) is in there somewhere already, so that's free. In integer math, you'll have all the usual rounding and rollover and sign extension issues to worry about. Still, it's not hard and works well. Done carefully, this will actually AC-couple the signal to an accuracy of a fraction of an LSB. John
Reply by ●April 12, 20052005-04-12
Hey Antti, Thanks a ton, the paper was too helpful. This kind of a design will improve my system performance by alot. Thanks MORPHEUS
Reply by ●April 12, 20052005-04-12
Reply by ●April 12, 20052005-04-12
"morpheus" <saurster@gmail.com> schrieb im Newsbeitrag news:1113328506.304806.220330@z14g2000cwz.googlegroups.com...> Hey Antti, > Thanks a ton, the paper was too helpful. This kind of a design will > improve my system performance by alot. > Thanks > MORPHEUS >:) thanks, I hoped it would be! It makes always sense to read very carfully all the stuff Ken Chapman writes! Tons of stuff to learn. I actually used that technique in 'digital carrier frequency amplifier' for SG bridge and LVDT sensors. It was using XC2S200E and microblaze and some digital path and simple filter etc.. Antti
Reply by ●April 12, 20052005-04-12
