The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virtex-4 also serializes and sends the least significant byte first. This is opposite of the format Virtex-II Pro devices used in sending the most significant byte first./* What does this really mean? Are the v2pro and v4 MGT's incompatible because of this? Will it work if the bit order is reversed before sending or after recieving? Jason
Connecting Virtex2pro to Virtex4 via RocketIO MGT's
Started by ●April 14, 2005
Reply by ●April 14, 20052005-04-14
Virtex-II Pro and Virtex-4 MGTs are compatible. This note simply refers to the necessary connections of the parallel TX/RX data bus between the fabric and the MGT. Ed jason.stubbs wrote:> The following extract from the Virtex 4 RIO user guide states: > > */Serialization/* > > */As in Virtex-II Pro X devices, Virtex-4 also serializes and sends the > least significant byte first. This is opposite of the format Virtex-II > Pro devices used in sending the most significant byte first./* > > What does this really mean? > > Are the v2pro and v4 MGT's incompatible because of this? > > Will it work if the bit order is reversed before sending or after > recieving? > > Jason >
Reply by ●April 14, 20052005-04-14
Ed, So, if I send data from a V2Pro to a V4 the MSB is sent first. when the V4 receives and deserializes the data, the MSB of the V2pro becomes the LSB of the V4? And if I send data from a V4 to a V2Pro the LSB is sent first. when the V2Pro receives and deserializes the data, the LSB of the V4 becomes the MSB of the V2Pro? If the bus order is inverted at one end of the link, everything should be OK? Jason
Reply by ●April 14, 20052005-04-14
jason.stubbs wrote:> Ed, > > So, if I send data from a V2Pro to a V4 the MSB is sent first. when > the V4 receives and deserializes the data, the MSB of the V2pro becomes > the LSB of the V4? > > And if I send data from a V4 to a V2Pro the LSB is sent first. when > the V2Pro receives and deserializes the data, the LSB of the V4 becomes > the MSB of the V2Pro? > > If the bus order is inverted at one end of the link, everything should > be OK? > > Jason >No, it's a byte ordering issue, not a bit ordering issue, so the order that the bytes are sent or received are different. V-II Pro V-II Pro X/V-4 1 Byte: [7:0] = [7:0] 2 Byte: [15:8][7:0] = [7:0][15:8] 4 Byte: [31:24][23:16][15:8][7:0] = [7:0][15:8][23:16][31:24] For example if you want to send the following bytes in the following order: Byte 1 = 0xDE Byte 2 = 0xAD Byte 3 = 0xBE Byte 4 = 0xEF In Virtex-II Pro TX/RXDATA[31:0] would be 0xDE_AD_BE_EF In Virtex-II Pro X TX/RXDATA[31:0] would be 0xEF_BE_AD_BE In Virtex-4 TX/RXDATA[31:0] would be 0xEF_BE_AD_BE Ed
Reply by ●April 14, 20052005-04-14
Ed, thanks, now its clear!! BTW, do you know when the Aurora core is going to be available for the V4? Cheers Jason
Reply by ●April 14, 20052005-04-14
Ed McGettigan wrote:> jason.stubbs wrote: > >> Ed, >> >> So, if I send data from a V2Pro to a V4 the MSB is sent first. when >> the V4 receives and deserializes the data, the MSB of the V2pro becomes >> the LSB of the V4? >> >> And if I send data from a V4 to a V2Pro the LSB is sent first. when >> the V2Pro receives and deserializes the data, the LSB of the V4 becomes >> the MSB of the V2Pro? >> >> If the bus order is inverted at one end of the link, everything should >> be OK? >> >> Jason >> > > No, it's a byte ordering issue, not a bit ordering issue, so > the order that the bytes are sent or received are different. > > V-II Pro V-II Pro X/V-4 > 1 Byte: [7:0] = [7:0] > 2 Byte: [15:8][7:0] = [7:0][15:8] > 4 Byte: [31:24][23:16][15:8][7:0] = [7:0][15:8][23:16][31:24] > > For example if you want to send the following bytes in the > following order: > > Byte 1 = 0xDE > Byte 2 = 0xAD > Byte 3 = 0xBE > Byte 4 = 0xEF > > In Virtex-II Pro TX/RXDATA[31:0] would be 0xDE_AD_BE_EF > In Virtex-II Pro X TX/RXDATA[31:0] would be 0xEF_BE_AD_BE > In Virtex-4 TX/RXDATA[31:0] would be 0xEF_BE_AD_BE > > Ed >One caveat with the above is that this is true for the encoded modes. In the case of non encoded (aka raw) bit ordering would be a complete LSB to MSB swap. Ed
