Odd Oversampling

Hi newsgroup,

maybe someone of you out there has faced some similar problem:

I want to sample 16MHz data with a 125MHz clock.

But 125/16 = 7.8125

Is there some tricky method to perform this kind of oversampling ?

The only thing I know is the Bresenham algorithm, but could that
be the solution ?

Thank you in advance.

Rgds

On 18 Apr 2005 03:03:25 -0700, ALuPin@web.de (ALuPin) wrote:


>I want to sample 16MHz data with a 125MHz clock.
>
>But 125/16 = 7.8125
>
>Is there some tricky method to perform this kind of oversampling ?

Why do you need any tricks?  You have at least 7 cycles of your
fast clock in which to sample each data point.  The samples will
be either 7 or 8 clocks apart.  So, you look at the 16MHz clock
and use it to create a clock-enable in the 125MHz clock domain.

If you don't have access to the original 16MHz clock, you can
either try to recover it by locking a digital PLL on to the 
data transitions (7x oversampling is *just* about enough
to be able to do this easily) or you can use dead-reckoning
by using a numerically-controlled oscillator (NCO) to generate
16MHz sampling pulses with a phase jitter.  And yes,
an NCO is effectively an implementation of Bresenham.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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The contents of this message may contain personal views which 
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ALuPin wrote:

> I want to sample 16MHz data with a 125MHz clock.
> Is there some tricky method to perform this kind of oversampling ?

There's a simple one if you have both clocks.
Write a synchronous process using 125MHz
as the clock and 16MHz as an input named "rate"
Synchronize "rate" and use it to generate a
rate_rising clock enable pulse.

               -- Mike Treseler

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:ft8761tdcb22fop7o910lkc8l5qlirhueg@4ax.com...
> If you don't have access to the original 16MHz clock, you can
> either try to recover it by locking a digital PLL on to the
> data transitions (7x oversampling is *just* about enough
> to be able to do this easily)

It's easy enough with just 4 times oversampling. XAPP224 shows how to do it
at 400Mb+ data rates.
Cheers, Syms.

On Mon, 18 Apr 2005 09:42:27 -0700, "Symon" <symon_brewer@hotmail.com>
wrote:

>"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote
[...]
>> 7x oversampling is *just* about enough
>> to be able to do this easily
>
>It's easy enough with just 4 times oversampling. XAPP224 shows how to do it
>at 400Mb+ data rates.

OK.  I was recalling bad memories of an attempt to do DPLL with only
4x oversampling in a system where the cheap-and-nasty fibre optic
transceivers introduced rather a lot of pulse width distortion, 
which made it a whole lot more difficult.

Thanks for the reference.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

"Symon" <symon_brewer@hotmail.com> wrote in message news:<4263e34f@x-privat.org>...
> "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
> news:ft8761tdcb22fop7o910lkc8l5qlirhueg@4ax.com...
> > If you don't have access to the original 16MHz clock, you can
> > either try to recover it by locking a digital PLL on to the
> > data transitions (7x oversampling is *just* about enough
> > to be able to do this easily)
> 
> It's easy enough with just 4 times oversampling. XAPP224 shows how to do it
> at 400Mb+ data rates.
> Cheers, Syms.
Please correct me if I got the problem wrong.

Is it right that I could define a counter (clocked with 125MHz)
and define one counter position as the sample point which is located
in the middle position neighborhood of the bit to sample ?
The counter would be quasi started if the first transition is
recognized. This transition could be recognized with a two stage flip
flop chain in the 125Mhz
clock domain.
The problem would be that the following sample points would walk
because
125/16 is a fraction number. Is that right ?

Could that sample point walk even then if the oversample factor 125/x
would
be an integer number for example 120MHz/12MHz when 120MHz having 0.05%
tolerance
and 20MHz having 0.02% tolerance ?


If I have 7 times oversampling  would I need then an input stage
with seven stages (XAPP224)? What additional clocks would I need then
?
Or are four clocks sufficient?

Thank you in advance.

Rgds
Andr&#4294967295;

One more question:

The quasi "oversample" solution in XAPP224 does imply that the sample
clock is the same as the clock from the incoming data stream.

But in my situation I have a clock that is 7-8 times faster.

Please clarify ...

Thank you.

Rgds
Andr�

Hi Andr�,
I'd probably  do it like this.
Have a 7 bit counter that counts modulo 125 on your 125MHz clock. Call it
'counter'. If you get a transition on the data (which you've already sampled
into the 125MHz clock domain, right?), reset it to 0. When the counter says
4 | 12 | 19 | 27 | 35 | 43 | 51 | 58 | 66 | 74| 82 | 90 | 97 | 105 | 113 |
121 sample the data. (I'd check those numbers for yourself, my arithmetic
isn't what it used to be..) Of course with half the bits there will be a
transition so you'll only be sampling at big counts if you get a lot of
consecutive equal bits. Remember if the count gets to 124 the next count
should be 0, i.e. modulo 125.
Have fun, Syms.

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0504180203.226a3d5b@posting.google.com...
> Hi newsgroup,
>
> maybe someone of you out there has faced some similar problem:
>
> I want to sample 16MHz data with a 125MHz clock.
>
> But 125/16 = 7.8125
>
> Is there some tricky method to perform this kind of oversampling ?
>
> The only thing I know is the Bresenham algorithm, but could that
> be the solution ?
>
> Thank you in advance.
>
> Rgds

Here is a circuit that generates 16 MHz from a 125 MHz clock:
Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
That gives you 80 MHz, which might be convenient for 5x oversampling.
Peter Alfke, Xilinx Applications

Personally I probably wouldn't do this, depending on the situation. I find
that having as few clocks as possible is the best strategy for FPGAs. I use
enables instead. So, if Andre already has a 125MHz system clock in his
device that he's using, he should stick with it rather than generating a new
clock domain. If, however, the 125MHz is only used in this circuit, I guess
making it into 80MHz might work.
YMMV, Syms.
p.s. I think all my numbers in that previous post were 1 too big for a
proper sync design.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:1113925710.027051.206960@f14g2000cwb.googlegroups.com...
> Here is a circuit that generates 16 MHz from a 125 MHz clock:
> Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
> That gives you 80 MHz, which might be convenient for 5x oversampling.
> Peter Alfke, Xilinx Applications
>