Ambigous operator '&'

HI all,

  While compiling my design in Quartus II 4.2 , I got following errors.
The piece of code is given below....

Error: VHDL error at Ctrl_Ram.Vhd(66): can't determine definition of
operator ""&"" -- found 2 possible definitions
Error: Verilog HDL or VHDL error at Ctrl_Ram.Vhd(66): Unconverted
VHDL-1402: ambiguous type: 'Regfile' or 'SIGNED'
Error: VHDL Type Conversion error at Ctrl_Ram.Vhd(66): can't determine
type of object or expression near text or symbol "UNSIGNED"
Error: Ignored construct Ctrl_Ram_Arch at Ctrl_Ram.Vhd(42) because of
previous errors


  -- These subtypes are in  a package....

 	subtype WORD   is signed(15 downto 0);
	subtype DWORD  is unsigned(31 downto 0);


-- In the Architecture declaration part I am defining follwing
signals..


  type Regfile is array (natural range<>) of WORD;
	signal Regfile_Ctrl_High : Regfile(0 to 15); -- High Bank Registe File
	signal Regfile_Ctrl_Low  : Regfile(0 to 15); -- Low Bank Register File

       signal data_out_high : WORD;
    signal data_out_low  : WORD;


-- And these are the concurrent statements in Architecture body...

 --  Regfile Read  Assignments
   data_out_low  <= Regfile_Ctrl_Low(TO_INTEGER(Addrs_In));
   data_out_high <= Regfile_Ctrl_High(TO_INTEGER(Addrs_In));

   -- Concatenation of Low and High to form 32 Control Word
   Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
THIS LINE...

Whats wrong with the last statment. I expect '&' operator to
concatenate the two signals. What could be the other meaning of '&'
operator.  I think I am doing a silly mistake some where . Please help
me in resolving this..

 Thanks.
-- Mohammed A Khader.

> 
>    -- Concatenation of Low and High to form 32 Control Word
>    Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
> THIS LINE...
> 

> 

-- just try
Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low);

regards,
laurent gauch
www.amontec.com

Thanks !  It Worked ..  But both are logically equal. What was my
mistake ?

On 20 Apr 2005 03:48:55 -0700, Mohammed  A khader wrote:

>    -- Concatenation of Low and High to form 32 Control Word
>    Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
> THIS LINE...
> 
> Whats wrong with the last statment. I expect '&' operator to
> concatenate the two signals. What could be the other meaning of '&'
> operator.  I think I am doing a silly mistake some where . Please help
> me in resolving this..

With '&' you can (1) concatenate two arrays. For example, when using two
arrays of std_login (aka std_logic_vector):
"000" & "111"
This will create a 6 element long array.
With '&' you can (2) append or (3) prepend a single element to an array:
"000" & '1'
'0' & "111"
This will create a 4 element long array. Note that it is syntactically
different from "0" & "111", which I described in (1).
With '&' you can (4) create a new array by concatenating two elements:
'0' & '1'
This will create a 2 element array.


Now, this works not only with std_logic_vector, but with any array. For
example, with this one:

>   type Regfile is array (natural range<>) of WORD;

Now we have two different interpretations of
  data_out_high & data_out_low
It can either produce a signed(0 to 31) (VHDL-93) according to (1), or a
Regfile(0 to 1) according to (4).


Laurent showed one way to avoid this problem. My first guess would have
been something like
   Data32_Out <= unsigned(signed(data_out_high) & signed(data_out_low));
which is closer to your original code. Maybe the following would work:
   Data32_Out <= unsigned(signed'(data_out_high & data_out_low));
But I'm not sure. (Please note the tick.)


[xp and f'up2 comp.lang.vhdl]

Sebastian