Virtex slow clock multiply options?

Hello,

Please forgive me if this is a rather elementary problem.  My situation
is this:  I'm using a Virtex Device (XVC800) I believe that has is
being clocked with a 40 MHz and 10 MHz signal.  Main goal: the FPGA
creates two output 'clock' signals with varying frequency ('user'
selected freq, 50% duty), one between 500 kHz and 700 kHz and the other
exactly 16 times the frequency of the first.  Also, of course, provide
the 'user' with as much selection of frequencies between 500 and 700
kHz as possible (i.e. small granularity).

Thinking about it, I can only think of one way to do this.  Feed the 40
MHz clock through two DLL's to provide a 160MHz signal.  Have the
'user' provide a count of the # of 160 MHz clock cycles requested to
create the 16x freq signal and then slow down the signal (multiply the
count by 16) to create the 500 to 700 kHz signal.  Doing this, the
'user' is only able to select 6 different frequencies that will match
the range between 500 and 700.

I would of course love to just create the 500 to 700 kHz signal off of
the 40 MHz clock (providing 23 different freq. selections) then somehow
use the DLLs or other to multiply by 16, but the DLLs have a min input
freq. of 25 MHz.

Anyone have any ideas?  Everyone thoroughly confused as to what I'm
trying to do?  Anyone still reading this far?  

Thanks a bunch,

Kevin

k...@firebolt.com wrote:
> Hello,
>
> Please forgive me if this is a rather elementary problem.  My
situation
> is this:  I'm using a Virtex Device (XVC800) I believe that has is
> being clocked with a 40 MHz and 10 MHz signal.  Main goal: the FPGA
> creates two output 'clock' signals with varying frequency ('user'
> selected freq, 50% duty), one between 500 kHz and 700 kHz and the
other
> exactly 16 times the frequency of the first.  Also, of course,
provide
> the 'user' with as much selection of frequencies between 500 and 700
> kHz as possible (i.e. small granularity).
>
> Thinking about it, I can only think of one way to do this.  Feed the
40
> MHz clock through two DLL's to provide a 160MHz signal.  Have the
> 'user' provide a count of the # of 160 MHz clock cycles requested to
> create the 16x freq signal and then slow down the signal (multiply
the
> count by 16) to create the 500 to 700 kHz signal.  Doing this, the
> 'user' is only able to select 6 different frequencies that will match
> the range between 500 and 700.
>
> I would of course love to just create the 500 to 700 kHz signal off
of
> the 40 MHz clock (providing 23 different freq. selections) then
somehow
> use the DLLs or other to multiply by 16, but the DLLs have a min
input
> freq. of 25 MHz.
>
> Anyone have any ideas?  Everyone thoroughly confused as to what I'm
> trying to do?  Anyone still reading this far?
>
> Thanks a bunch,
>
> Kevin


This is simple and nothing new.  Google for "DDS" or Direct Digital
Synthesis.
There are a few threads in this group on the subject.

Please correct me if I'm wrong (probable), but aren't DSS's used just
to create the numeric representation of a requested wave-shape.  Sorry
I didn't clarify in my original post, I only need to output a square
wave (0/1) over the standard FPGA I/O.  As I would still be clocking
the DSS at 40 MHz, I wouldn't be able to get better
resolution/granularity for frequencies between 500 to 700 kHz that
would be able to be multiplied by 16 based on a 40 MHz clock  Is there
a way to make the DSS asynchronous?  Sorry if I'm missing something
obvious.

Kevin

You take your reference clock and multiply it with the DCM to somthing
like 100MHz, or a little more.
From there you can do digital synthesis that results in 10ns jitter at
the output. You have two options to reduce that jitter:
1. Instead of a square wave use an DAC to generate a sine wave and
filter it with a low pass filer.
2. Use an external PLL to remove the jitter.

If I rember correctly Peter Alfke told me that the DCM succeeds to
reduce the jitter down to about 100ps so you could get rid of the
external PLL and instead synthesize a clock that is an integer multiple
of the target clock but is fast enough to be fed into a DCM and than
devide the result down to the target frequency.

Square wave synthesis is done with Bresenhams line drawing algorithm (X
counts with the input frequency and the output square wave is the lowest
bit of Y)
Sine wave synthesis is only marginally more complex but requires more
resources.

Kolja Sulimma

kevin@firebolt.com wrote:
> Please correct me if I'm wrong (probable), but aren't DSS's used just
> to create the numeric representation of a requested wave-shape.  Sorry
> I didn't clarify in my original post, I only need to output a square
> wave (0/1) over the standard FPGA I/O.  As I would still be clocking
> the DSS at 40 MHz, I wouldn't be able to get better
> resolution/granularity for frequencies between 500 to 700 kHz that
> would be able to be multiplied by 16 based on a 40 MHz clock  Is there
> a way to make the DSS asynchronous?  Sorry if I'm missing something
> obvious.
> 
> Kevin
> 

kevin@firebolt.com wrote:

>Please correct me if I'm wrong (probable), but aren't DSS's used just
>to create the numeric representation of a requested wave-shape.  Sorry
>I didn't clarify in my original post, I only need to output a square
>wave (0/1) over the standard FPGA I/O.  As I would still be clocking
>the DSS at 40 MHz, I wouldn't be able to get better
>resolution/granularity for frequencies between 500 to 700 kHz that
>would be able to be multiplied by 16 based on a 40 MHz clock  Is there
>a way to make the DSS asynchronous?  Sorry if I'm missing something
>obvious.
>
>Kevin
>
>  
>
Not quite.  You just need the phase accumulator portion of a DDS.  the 
most significant bit out is your square wave output.  The output will 
have a jitter of at most +/- 1 period of you master clock.

This is basically an accumulator to which you add a fixed increment on 
each clock.  A k bit accumulator with an increment value of N will 
overflow (ie lap) N times in 2^k clocks.  For example, if the 
accumulator is 4 bits and it is incremented by 1, it takes 16 clocks to 
overflow, so once in 16 clocks.  If instead the increment value is 5 it 
overflows 5 times in 16 clocks following this sequence:
0
5
10
15
4
9
14
3
8
13
2
7
12
1
6
11
0

Note that if you take only the MSB out, you get the equivalent of a 
sampled squarewave.

Increasing the number of bits increases the frequency resolution.  
Increasing the master clock frequency reduces the maximum jitter.

The output frequency is  Fo= Fclk * N/(2^k).  N is a 2's complement 
value, so if the msb is set, you get negative frequency (ie the rotation 
is in the opposite direction).

In the case of a classic DDS, some number of the MSBs from this phase 
accumulator feed a phase to amplitude converter, which might be a ROM, a 
cordic rotator, or some algorithmic hardware to convert the phase angle 
(which is the fractional part of a revolution) to the desired waveshape, 
which is typically sine and cosine.

Hope this helps.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

"Hope this helps."

It absolutely does!  Thanks guys.

Kevin

Ray Andraka wrote:
> kevin@firebolt.com wrote:
>
> >Please correct me if I'm wrong (probable), but aren't DSS's used
just
> >to create the numeric representation of a requested wave-shape.
Sorry
> >I didn't clarify in my original post, I only need to output a square
> >wave (0/1) over the standard FPGA I/O.  As I would still be clocking
> >the DSS at 40 MHz, I wouldn't be able to get better
> >resolution/granularity for frequencies between 500 to 700 kHz that
> >would be able to be multiplied by 16 based on a 40 MHz clock  Is
there
> >a way to make the DSS asynchronous?  Sorry if I'm missing something
> >obvious.
> >
> >Kevin
> >
> >
> >
> Not quite.  You just need the phase accumulator portion of a DDS.
the
> most significant bit out is your square wave output.  The output will

> have a jitter of at most +/- 1 period of you master clock.
>
> This is basically an accumulator to which you add a fixed increment
on
> each clock.  A k bit accumulator with an increment value of N will
> overflow (ie lap) N times in 2^k clocks.  For example, if the
> accumulator is 4 bits and it is incremented by 1, it takes 16 clocks
to
> overflow, so once in 16 clocks.  If instead the increment value is 5
it
> overflows 5 times in 16 clocks following this sequence:
> 0
> 5
> 10
> 15
> 4
> 9
> 14
> 3
> 8
> 13
> 2
> 7
> 12
> 1
> 6
> 11
> 0
>
> Note that if you take only the MSB out, you get the equivalent of a
> sampled squarewave.
>
> Increasing the number of bits increases the frequency resolution.
> Increasing the master clock frequency reduces the maximum jitter.
>
> The output frequency is  Fo= Fclk * N/(2^k).  N is a 2's complement
> value, so if the msb is set, you get negative frequency (ie the
rotation
> is in the opposite direction).
>
> In the case of a classic DDS, some number of the MSBs from this phase

> accumulator feed a phase to amplitude converter, which might be a
ROM, a
> cordic rotator, or some algorithmic hardware to convert the phase
angle
> (which is the fractional part of a revolution) to the desired
waveshape,
> which is typically sine and cosine.
>
> Hope this helps.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote:

> "Hope this helps."
> 
> It absolutely does!  Thanks guys.
> 
> Kevin
> 

Keep in mind that the output of this type of DDS will NOT produce a 50%
duty cycle (which is something you asked for), except at frequencies whose
period is an even number of counts of the master clock (i.e., Fmaster/2N).
For other frequencies, the maximum deviation from 50% duty cycle is one
master clock. For example, if you tried to go output 75 MHz, with a master
clock of 160 MHz, you would have a series of 125 ns periods with an
occasional high or low stretched out by an extra 62.5 ns to keep the
average frequency on track.

Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher
if you can) then implement a 32-bit phase accumulator, you should be close
enough to 50% duty cycle and have small enough frequency steps to make
most people happy.

One way to reduce the jitter a little is to use a DAC type of approach,
and a little bit of analog circuitry. You would take, say the 4 most
significant bits of the phase output, and feed them to a phase to
amplitude lookup table, then feed the output of the lookup table to a
series of outputs with well-chosen resistor values.

The resistor values would be, for example, 200, 400, 800 and 1600, Ohms.
Of course, those resistor values don't exist. So you would pick the
closest ones you can. These resistors would then all be connected
together. This common node, then, would be your analog output. You could
buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass
filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all
things considered. The sine wave could then go to a comparator, and the
comparator output would have much lower jitter than you would if you
didn't use any analog techniques. This 9-11 MHz digital signal would be
the x16 signal, and you would create the base signal by dividing it down.

Total external parts: 4 resistors, 1 package with two or four op-amps, one
comparator, and a few capacitors. If you used a quad op-amp, you could
make a really good low-pass filter, and really cut the jitter down.

If this all sounds like too much complication and bother, well, it
probably is, but then again, maybe it will appeal to you (or the customer.)

Of course, you could also use a DAC instead of the four resistors. You
could even use an 8-bit DAC which would really help cut down the jitter,
but would force you to implement an 8-bit output phase to amplitude
converter.

And the ultimate would be to put an Analog Devices DDS on the board. Then
you would use the FPGA to generate the 160 MHz clock, program the DDS, and
divide down the frequency output of the DDS by 16. That is what I would do.

--Mac


> Ray Andraka wrote:
>> kevin@firebolt.com wrote:
>>
>> >Please correct me if I'm wrong (probable), but aren't DSS's used
> just
>> >to create the numeric representation of a requested wave-shape.
> Sorry
>> >I didn't clarify in my original post, I only need to output a square
>> >wave (0/1) over the standard FPGA I/O.  As I would still be clocking
>> >the DSS at 40 MHz, I wouldn't be able to get better
>> >resolution/granularity for frequencies between 500 to 700 kHz that
>> >would be able to be multiplied by 16 based on a 40 MHz clock  Is
> there
>> >a way to make the DSS asynchronous?  Sorry if I'm missing something
>> >obvious.
>> >
>> >Kevin
>> >
>> >
>> >
>> Not quite.  You just need the phase accumulator portion of a DDS.
> the
>> most significant bit out is your square wave output.  The output will
> 
>> have a jitter of at most +/- 1 period of you master clock.
>>
>> This is basically an accumulator to which you add a fixed increment
> on
>> each clock.  A k bit accumulator with an increment value of N will
>> overflow (ie lap) N times in 2^k clocks.  For example, if the
>> accumulator is 4 bits and it is incremented by 1, it takes 16 clocks
> to
>> overflow, so once in 16 clocks.  If instead the increment value is 5
> it
>> overflows 5 times in 16 clocks following this sequence:
>> 0
>> 5
>> 10
>> 15
>> 4
>> 9
>> 14
>> 3
>> 8
>> 13
>> 2
>> 7
>> 12
>> 1
>> 6
>> 11
>> 0
>>
>> Note that if you take only the MSB out, you get the equivalent of a
>> sampled squarewave.
>>
>> Increasing the number of bits increases the frequency resolution.
>> Increasing the master clock frequency reduces the maximum jitter.
>>
>> The output frequency is  Fo= Fclk * N/(2^k).  N is a 2's complement
>> value, so if the msb is set, you get negative frequency (ie the
> rotation
>> is in the opposite direction).
>>
>> In the case of a classic DDS, some number of the MSBs from this phase
> 
>> accumulator feed a phase to amplitude converter, which might be a
> ROM, a
>> cordic rotator, or some algorithmic hardware to convert the phase
> angle
>> (which is the fractional part of a revolution) to the desired
> waveshape,
>> which is typically sine and cosine.
>>
>> Hope this helps.
>>
>> --
>> --Ray Andraka, P.E.
>> President, the Andraka Consulting Group, Inc.
>> 401/884-7930     Fax 401/884-7950
>> email ray@andraka.com
>> http://www.andraka.com
>>
>>  "They that give up essential liberty to obtain a little
>>   temporary safety deserve neither liberty nor safety."
>>                                           -Benjamin Franklin, 1759

Mac wrote:

>On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote:
>
>  
>
>>"Hope this helps."
>>
>>It absolutely does!  Thanks guys.
>>
>>Kevin
>>
>>    
>>
>
>Keep in mind that the output of this type of DDS will NOT produce a 50%
>duty cycle (which is something you asked for), except at frequencies whose
>period is an even number of counts of the master clock (i.e., Fmaster/2N).
>For other frequencies, the maximum deviation from 50% duty cycle is one
>master clock. For example, if you tried to go output 75 MHz, with a master
>clock of 160 MHz, you would have a series of 125 ns periods with an
>occasional high or low stretched out by an extra 62.5 ns to keep the
>average frequency on track.
>
>Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher
>if you can) then implement a 32-bit phase accumulator, you should be close
>enough to 50% duty cycle and have small enough frequency steps to make
>most people happy.
>
>One way to reduce the jitter a little is to use a DAC type of approach,
>and a little bit of analog circuitry. You would take, say the 4 most
>significant bits of the phase output, and feed them to a phase to
>amplitude lookup table, then feed the output of the lookup table to a
>series of outputs with well-chosen resistor values.
>
>The resistor values would be, for example, 200, 400, 800 and 1600, Ohms.
>Of course, those resistor values don't exist. So you would pick the
>closest ones you can. These resistors would then all be connected
>together. This common node, then, would be your analog output. You could
>buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass
>filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all
>things considered. The sine wave could then go to a comparator, and the
>comparator output would have much lower jitter than you would if you
>didn't use any analog techniques. This 9-11 MHz digital signal would be
>the x16 signal, and you would create the base signal by dividing it down.
>
>Total external parts: 4 resistors, 1 package with two or four op-amps, one
>comparator, and a few capacitors. If you used a quad op-amp, you could
>make a really good low-pass filter, and really cut the jitter down.
>
>If this all sounds like too much complication and bother, well, it
>probably is, but then again, maybe it will appeal to you (or the customer.)
>
>Of course, you could also use a DAC instead of the four resistors. You
>could even use an 8-bit DAC which would really help cut down the jitter,
>but would force you to implement an 8-bit output phase to amplitude
>converter.
>
>And the ultimate would be to put an Analog Devices DDS on the board. Then
>you would use the FPGA to generate the 160 MHz clock, program the DDS, and
>divide down the frequency output of the DDS by 16. That is what I would do.
>
>--Mac
>
>  
>
 for many applications, using an external circuit such as a DAC or AD 
DDS would be extreme overkill.  One such overkill application would be 
generation of a clock for a UART.

One way to look at the output of the pahse accumulator I described 
earlier is that it is  a perfect squarewave resampled by your master 
clock.  If the master clock is not a neat multiple of your generated 
frequency, then you'll have jitter of up to a clock cycle.  You can 
reduce the jitter by using a faster master clock (with modern FPGAs 
there is no reason you couldn't quadruple your 40 MHz master clock and 
run the DDS at 160 MHz).

It all comes down to what are your requirements for the generated clock.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Ray Andraka wrote:

> >
>  for many applications, using an external circuit such as a DAC or AD

> DDS would be extreme overkill.  One such overkill application would
be
> generation of a clock for a UART.
>
> One way to look at the output of the pahse accumulator I described
> earlier is that it is  a perfect squarewave resampled by your master
> clock.  If the master clock is not a neat multiple of your generated
> frequency, then you'll have jitter of up to a clock cycle.  You can
> reduce the jitter by using a faster master clock (with modern FPGAs
> there is no reason you couldn't quadruple your 40 MHz master clock
and
> run the DDS at 160 MHz).
>
> It all comes down to what are your requirements for the generated
clock.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Another issue with the analog approach is that you can introduce more
jitter into the system if your power supplies are not clean.  This
occurs when the threshold varies for creating a squarewave from the
synthesized waveform.  Voltage jitter in the threshold is converted
to time jitter.  The time jitter increases as the slew rate of the
synthesized wave decreases.  If your synthesized waveform is not
produced by a D/A with a solid reference voltage, but rather the
LVCMOS outputs of the FPGA through resistors, you'll get voltage
jitter in the synthesized waveform as well due to noise on Vcco.

Duty cycle is also not as easy to control in the analog approach,
although you can deal with this by synthesizing a 2x frequency and
dividing by two afterwards.  When using the output of a DDS directly
remember that the MSB of the phase counter is only 50% when the
counter wraps at a power of 2.  While this is the easiest way to
make a DDS, there are applications where the count is not a power
of 2 to allow a precise frequency step.

On Thu, 28 Apr 2005 14:50:27 -0400, Ray Andraka wrote:

> Mac wrote:
> 
>>On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote:
>>
>>  
>>
>>>"Hope this helps."
>>>
>>>It absolutely does!  Thanks guys.
>>>
>>>Kevin
>>>
>>>    
>>>
>>
>>Keep in mind that the output of this type of DDS will NOT produce a 50%
>>duty cycle (which is something you asked for), except at frequencies whose
>>period is an even number of counts of the master clock (i.e., Fmaster/2N).
>>For other frequencies, the maximum deviation from 50% duty cycle is one
>>master clock. For example, if you tried to go output 75 MHz, with a master
>>clock of 160 MHz, you would have a series of 125 ns periods with an
>>occasional high or low stretched out by an extra 62.5 ns to keep the
>>average frequency on track.
>>
>>Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher
>>if you can) then implement a 32-bit phase accumulator, you should be close
>>enough to 50% duty cycle and have small enough frequency steps to make
>>most people happy.
>>
>>One way to reduce the jitter a little is to use a DAC type of approach,
>>and a little bit of analog circuitry. You would take, say the 4 most
>>significant bits of the phase output, and feed them to a phase to
>>amplitude lookup table, then feed the output of the lookup table to a
>>series of outputs with well-chosen resistor values.
>>
>>The resistor values would be, for example, 200, 400, 800 and 1600, Ohms.
>>Of course, those resistor values don't exist. So you would pick the
>>closest ones you can. These resistors would then all be connected
>>together. This common node, then, would be your analog output. You could
>>buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass
>>filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all
>>things considered. The sine wave could then go to a comparator, and the
>>comparator output would have much lower jitter than you would if you
>>didn't use any analog techniques. This 9-11 MHz digital signal would be
>>the x16 signal, and you would create the base signal by dividing it down.
>>
>>Total external parts: 4 resistors, 1 package with two or four op-amps, one
>>comparator, and a few capacitors. If you used a quad op-amp, you could
>>make a really good low-pass filter, and really cut the jitter down.
>>
>>If this all sounds like too much complication and bother, well, it
>>probably is, but then again, maybe it will appeal to you (or the customer.)
>>
>>Of course, you could also use a DAC instead of the four resistors. You
>>could even use an 8-bit DAC which would really help cut down the jitter,
>>but would force you to implement an 8-bit output phase to amplitude
>>converter.
>>
>>And the ultimate would be to put an Analog Devices DDS on the board. Then
>>you would use the FPGA to generate the 160 MHz clock, program the DDS, and
>>divide down the frequency output of the DDS by 16. That is what I would do.
>>
>>--Mac
>>
>>  
>>
>  for many applications, using an external circuit such as a DAC or AD 
> DDS would be extreme overkill.  One such overkill application would be 
> generation of a clock for a UART.
> 

The OP didn't say all that much about what he is trying to do. It is
a pretty good surmise, since he is talking about generating two
clocks, one of which is 16x the other, that he is generating clocks
for a UART. On the other hand, these clocks are much faster than
typical UART clocks for RS-232, so who knows?


> One way to look at the output of the pahse accumulator I described 
> earlier is that it is  a perfect squarewave resampled by your master 
> clock.  If the master clock is not a neat multiple of your generated 
> frequency, then you'll have jitter of up to a clock cycle.

I think that is exactly what I said, isn't it? Anyway, I am fairly
familiar with how dds's and phase accumulators work, and have even
incorporated a phase accumulator into an FPGA design, exactly as you
outline.

> You can 
> reduce the jitter by using a faster master clock (with modern FPGAs 
> there is no reason you couldn't quadruple your 40 MHz master clock and 
> run the DDS at 160 MHz).
> 

Yeah, that is what I said. So your max deviation from 50% duty cycle is
6.25 ns. The OP needs to generate 700 KHz * 16 = 11.2 MHz, which is a
period of around 90 ns. So a deviation of 6.25 ns is significant. That's
what got me thinking about ways to reduce the jitter.

> It all comes down to what are your requirements for the generated clock.

Well, he said 50% duty cycle. If you have a low of 7 clock periods
followed by a high of 8 clock periods (or vice-versa), I wouldn't exactly
call that a 50% duty cycle.

--Mac