Virtex slow clock multiply options?

On Thu, 28 Apr 2005 13:24:29 -0700, Gabor wrote:

> 
> Ray Andraka wrote:
> 
>> >
>>  for many applications, using an external circuit such as a DAC or AD
> 
>> DDS would be extreme overkill.  One such overkill application would
> be
>> generation of a clock for a UART.
>>
>> One way to look at the output of the pahse accumulator I described
>> earlier is that it is  a perfect squarewave resampled by your master
>> clock.  If the master clock is not a neat multiple of your generated
>> frequency, then you'll have jitter of up to a clock cycle.  You can
>> reduce the jitter by using a faster master clock (with modern FPGAs
>> there is no reason you couldn't quadruple your 40 MHz master clock
> and
>> run the DDS at 160 MHz).
>>
>> It all comes down to what are your requirements for the generated
> clock.
>>
>> --
>> --Ray Andraka, P.E.
>> President, the Andraka Consulting Group, Inc.
>> 401/884-7930     Fax 401/884-7950
>> email ray@andraka.com
>> http://www.andraka.com
>>
>>  "They that give up essential liberty to obtain a little
>>   temporary safety deserve neither liberty nor safety."
>>                                           -Benjamin Franklin, 1759
> 
> Another issue with the analog approach is that you can introduce more
> jitter into the system if your power supplies are not clean.  This
> occurs when the threshold varies for creating a squarewave from the
> synthesized waveform.  Voltage jitter in the threshold is converted
> to time jitter.

You did read the part where I said I would low-pass filter the output,
right?

> The time jitter increases as the slew rate of the
> synthesized wave decreases.  If your synthesized waveform is not
> produced by a D/A with a solid reference voltage, but rather the
> LVCMOS outputs of the FPGA through resistors, you'll get voltage
> jitter in the synthesized waveform as well due to noise on Vcco.
> 

I concede that this is all true.

> Duty cycle is also not as easy to control in the analog approach,
> although you can deal with this by synthesizing a 2x frequency and
> dividing by two afterwards.  When using the output of a DDS directly
> remember that the MSB of the phase counter is only 50% when the
> counter wraps at a power of 2.  While this is the easiest way to
> make a DDS, there are applications where the count is not a power
> of 2 to allow a precise frequency step.

I'm not sure I'm really following you here. The way a complete DDS works
is that there is a phase accumulator, followed by a phase to amplitude
converter (not sure if that is the proper name for it), followed by a DAC.
Which would have to be followed by a low-pass filter.

The phase accumulator, which has N bits, is incremented by a frequency
tuning word (FTW) every clock cycle. I think what you are saying is that
if and only if the FTW is a power of 2, the nominal duty cycle is exactly
50%.

If so, I think I agree with you.

I think you are also pointing out that a DDS can be tuned to any frequency
from DC to Fmaster/2, and the frequency step size is Fmaster/2^N. If so I
also agree with that.

Anyway, I'm getting tired of this. I'm sure the OP has enough ideas to get
going. I think if I have accomplished anything it is just muddying the
waters.  ;-)

--Mac