Forums

signals in modelsim

Started by Unknown April 29, 2005
Hi,

how can I add internal signals to the wave output of modelsim?

At the moment I have to add all the debug sinals to the port of my main 
entity.

Another question is, if its possible to save the modelsim settings 
somehow? (wave repesentation as integer, scale, etc...)

Do I have to close Modelsim everytime I resynthesize my uut?

regards,
Benjamin
Benjamin Menk�c wrote:

> Hi, > > how can I add internal signals to the wave output of modelsim? >
Add wave * (use -r for recursive if you like the mess or do trivial things)
> At the moment I have to add all the debug sinals to the port of my main > entity.
Use drag & drop, can do from a whole instance, very handy
> > Another question is, if its possible to save the modelsim settings > somehow? (wave repesentation as integer, scale, etc...)
Click on the save button ! (will create wave.do, editable etc)
> > Do I have to close Modelsim everytime I resynthesize my uut?
Synthesis has nothing to do with ModelSim if you do RTL sim. vcom does compile, restart -f suffient usually.
> > regards, > Benjamin
The simulator's (on-line) manual is probably a good starting point, maybe even faster than the newsgroup ;-)
ooops, forgot to sign.

RTFM.

Bert Cuzeau
Under the sim tab in the workspace box, a complete design hierarchy is
present.  You can browse through all of your sub-modules.  If you want
to add all signals for a sub-module into the wave you can simply drag
the sub module.  Otherwise, you can click on the sub-module and lookin
the objects pane.  It has all of the signals in that module.  You can
select all of the signals you want to add by ctrl+clicking each of
them, then you can add them to the wave by going to add menu -> wave ->
selected signals.  Also, you can drag the signals from the objects pane
straight to the wave window.

Yes you can save the waveform settings.  You click the save button
while the waveform pane is selected.  It saves to a .do file.  A .do
file is just a script file that you can run when you want to restore
those settings.  It's not automatic, but next time you load the project
you can type in the console do wave.do (or whatever you saved it as).

No you don't have to close Modelsim everytime you resynthesize.  You
just need to recompile (by going to the project tab of the workspace
and right clicking and choosing the appropriate compile command) and
then restart the simulation.

I hope that helped (though it appears other people have replied
already)

-Arlen

Hi,

my problem is that behavior simulation doesnt work somehow. Therefore I 
have to do post-translate simulation. However during translation XST 
doesnt keep the net-names, so its a little bit hard to find the right 
net in modelsim, I don't even know which net to take. Do I have to pick 
the right net using fpga-editor? Or how do I get an overview over the 
new nets?

regards,
Benjamin
You are going the wrong direction !


Benjamin Menk�c wrote:
> Hi, > > my problem is that behavior simulation doesnt work somehow.
Why ? Understand what doesn't work and fix it ! Don't synthesize RTL code which doesn't even simulate... Do you hope synthesis will miraculously "fix" a bad description ? The usual question is : "my RTL works (simulates ok) but the chip doesn't". > Therefore I have to do post-translate simulation. I knew it was not for a good reason. > However during translation It's not a translation. It's synthesis. XST infers physical hardware on which it tries to map the behavior you've described in RTL. Garbage in -> Garbage out. > XST doesnt keep the net-names, so its a little bit hard to find the right
> net in modelsim, I don't even know which net to take. Do I have to pick > the right net using fpga-editor? Or how do I get an overview over the > new nets?
You should do as suggested by all the experienced designers : - Learn synchronous design. - Make sure you understand how VHDL works. - Write good quality RTL, follow the rules mentioned. - Make a very quick synthesis pass to uncover usual mistakes Focus on reports, warnings, and chase down words like "asynchronous", "combinational" "feedback" "loop" "latch" etc... - Write good (reliable, self testing, documented, reuseable...) test benches. - Simulate carefully the RTL code - Do a careful synthesis - If the design is challenging timing-wise, do a unitary P&R and verify the actual timing figures with Static Timing Analysis. There is usually no need to perform timing sim, for reasons outside the scope of this post (and for the complexity level you are targeting). * A little time spent with the tools' documentation is a good investment. * Analyze known good code and understand how the design it was implemented and why. Re-inventing the wheel has its virtues, but it takes time... And no : don't open ISE's JC VHDL examples projects ;-) Bert Cuzeau
Hi,

simulating behavior doesnt work. Modelsim gives me this:

# ** Error: (vsim-3170) Could not find 'work.uut'.
# Error loading design
# Error: Error loading design

with exactly the same configuration, simulating Post-Translate, Post-Map 
and Post-Place all work. My testbench is instantiated as uut.

regards,
Benjamin
Hi Gallen,

it helped.

regards,
Benjamin
Benjamin Menk�c wrote:
> Hi, > > simulating behavior doesnt work. Modelsim gives me this: > > # ** Error: (vsim-3170) Could not find 'work.uut'. > # Error loading design > # Error: Error loading design > > with exactly the same configuration, simulating Post-Translate, Post-Map > and Post-Place all work. My testbench is instantiated as uut.
You are going way off track in your approach. Modelsim has really bad error messages. The error message you got is a catch all error message :-). In all probability there is small mistake in syntax or settings. 1) One does not instantiate a test bench. Test bench is a place holder for your enitity under test and logic required to test the entity. "My testbench is instantiated as uut." did you mean that you have named your testbench as "uut"? 2) Did your test bench compile without any errors?
> > regards, > Benjamin
Hi Brijesh,

Post-Translate Simulation works. However Behavioral Model simulation 
still doesn't.

> 1) One does not instantiate a test bench. Test bench is a place holder > for your enitity under test and logic required to test the entity. > "My testbench is instantiated as uut." did you mean that you have named > your testbench as "uut"?
my testbench is instantiated like this: ... -- Instantiate the Unit Under Test (UUT) uut: led_test PORT MAP( ... Under properties in the Project Navigator I have entered UUT as instance name. (it works for the other types of simulation).
> > 2) Did your test bench compile without any errors?
since I have inserted a SRL16, it hangs now SRL16_inst : SRL16 generic map ( INIT => X"0000") port map ( Q => dcm3_rst, -- SRL data output A0 => '1', -- Select[0] input A1 => '1', -- Select[1] input A2 => '0', -- Select[2] input A3 => '0', -- Select[3] input CLK => clk_ibufg, -- Clock input D => not lvds_locked -- SRL data input ); <-- in this line the error message is # -- Compiling architecture behavioral of led_test # ** Error: led_test.vhd(475): The actual for formal 'd' is not a globally static expression. regards, Benjamin