signals in modelsim

Benjamin Menk�c wrote:
> Hi Brijesh,
> 
> Post-Translate Simulation works. However Behavioral Model simulation 
> still doesn't.
> 
>> 1) One does not instantiate a test bench. Test bench is a place holder 
>> for your enitity under test and logic required to test the entity.
>> "My testbench is instantiated as uut." did you mean that you have 
>> named your testbench as "uut"?
> 
> 
> my testbench is instantiated like this:
> ...
>     -- Instantiate the Unit Under Test (UUT)
>     uut: led_test PORT MAP(
> ...
> Under properties in the Project Navigator I have entered UUT as instance 
>  name. (it works for the other types of simulation).
> 
>>
>> 2) Did your test bench compile without any errors?
> 
> 
> since I have inserted a SRL16, it hangs now
> SRL16_inst : SRL16
>    generic map (
>       INIT => X"0000")
>    port map (
>       Q => dcm3_rst,       -- SRL data output
>       A0 => '1',     -- Select[0] input
>       A1 => '1',     -- Select[1] input
>       A2 => '0',     -- Select[2] input
>       A3 => '0',     -- Select[3] input
>       CLK => clk_ibufg,   -- Clock input
>       D => not lvds_locked        -- SRL data input
>    );    <-- in this line
> 
> the error message is
> # -- Compiling architecture behavioral of led_test
> # ** Error: led_test.vhd(475): The actual for formal 'd' is not a 
> globally static expression.

Modelsim is very picky, it does not what you did to the D input
 >       D => not lvds_locked        -- SRL data input

You inverted the signal during port mapping. It does not like that.

Try something like

lvds_locked_N <= not lvds_locked;

then use the lvds_locked_N in the port mapping.





> 
> regards,
> Benjamin