Gated clock problem

I posted following message, but nobody respond(I don't know the reason, maybe it is too naive). I I post it here again, wish someone could help me.

I am using VirtexE to communication with an ADI's chip. The interface include, write, read, Data, and Address. I wish FPGA communication with the chip on FPGA main clock, which is up to 65MHz. I used a synchronized signal gated with the Clock to generate the write, read signal. Data and Address signal are synchronized. The problem is: 1) write/read signal often generate one more period than what I needed. although I could overcome it by adjust control signal's edge sensitivity, but it maybe reappear when I resynthesize the design. The reason is time delay of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Can I limit delay difference of the 2 inputs to an acceptable level? if it is, How could I do? 2) the timing of address, data and write/read is inconsistent with the timing required by ADI. I could delay some signal by add buffers or invertors. But I am afraid if it is work well if I add this modular to the top design. Is there any better way?

if I generate the w/r signal synchronized with the clock, the problem may do not exist. But I should drive the clock twice high, I don't know if VirtexE can work well on 125MHz.

Thank you for your advice.

Your design sounds like it *should* be a simple interface where you need
both devices to have compatible clock-to-out and in-to-clock setup times.
Is there something that makes this system less simple?  Are you running the
ADI chip from something that *isn't* the 65 MHz FPGA clock?  Or does the ADI
chip provide an interface that ISN'T relative to the ADI clock?

Your subject is "gated clock problem" but you only loosely talk about clock
and control propagation through a LUT.  Are you generating a gated clock for
the ADI device?  If so, does the control signal always change from a "valid
clock" to an "invalid clock" state leaving the clock level the same?  If the
rising edge of the clock registers the enable, the "gating" should be done
at the high level; turning off the clock by forcing it low *when it is high*
will give you a "runt pulse" that could mess up your system.

I'm guessing here because your detail is limited - it's not clear what
signals are a problem, what clocking is used, or what the I/O requirements
are.


"Wenju Fu" <fwj@nmrs.ac.cn> wrote in message
news:ee8dffe.-1@webx.sUN8CHnE...
> I posted following message, but nobody respond(I don't know the reason,
maybe it is too naive). I I post it here again, wish someone could help me.
>
> I am using VirtexE to communication with an ADI's chip. The interface
include, write, read, Data, and Address. I wish FPGA communication with the
chip on FPGA main clock, which is up to 65MHz. I used a synchronized signal
gated with the Clock to generate the write, read signal. Data and Address
signal are synchronized. The problem is: 1) write/read signal often generate
one more period than what I needed. although I could overcome it by adjust
control signal's edge sensitivity, but it maybe reappear when I resynthesize
the design. The reason is time delay of 2 inputs(one is clock, one is
control signal) of the LUT4 vary greatly. Can I limit delay difference of
the 2 inputs to an acceptable level? if it is, How could I do? 2) the timing
of address, data and write/read is inconsistent with the timing required by
ADI. I could delay some signal by add buffers or invertors. But I am afraid
if it is work well if I add this modular to the top design. Is there any
better way?
>
> if I generate the w/r signal synchronized with the clock, the problem may
do not exist. But I should drive the clock twice high, I don't know if
VirtexE can work well on 125MHz.
>
> Thank you for your advice.

"Wenju Fu" <fwj@nmrs.ac.cn> wrote in message
news:ee8dffe.-1@webx.sUN8CHnE...
> I posted following message, but nobody respond(I don't know the reason,
maybe it is too naive). I I post it here again, wish someone could help me.
>
No-one responded because gated clocks are anathema to this newsgroup! Don't
gate the clock. No, really, don't. You could consider gating the outputs of
FFs clocked on opposite edges to get what you want, but after considering
it, don't do that either.
The answer is to double your clock with a DLL, and your problems will melt
away!
Cheers, Syms.
p.s. Don't gate clocks.

Hello,

first, whatever you do, avoid gated clocks at all cost, especially in cases 
like you have.
I am not sure that i understand exactly what you would like to do, but what 
you should probably do is:

(1) Either increase the synchronizing clock  (125 MHz will run on VirtexE, 
but this is close to maximum (LUT-level),
 i.e.timing constraints must be very thorough). Personally, i would not go 
for this one.
(2) Just create an asynchronous interface, i.e. your "write" strobe is your 
clock and the "read" strobe is the read clock.
But this is more like spplication-specific, depends what exactly you'd like 
to do.

if you could give more details...
hope this helps.

regards,
Vladislav


"Wenju Fu" <fwj@nmrs.ac.cn> wrote in message 
news:ee8dffe.-1@webx.sUN8CHnE...
>I posted following message, but nobody respond(I don't know the reason, 
>maybe it is too naive). I I post it here again, wish someone could help me.
>
> I am using VirtexE to communication with an ADI's chip. The interface 
> include, write, read, Data, and Address. I wish FPGA communication with 
> the chip on FPGA main clock, which is up to 65MHz. I used a synchronized 
> signal gated with the Clock to generate the write, read signal. Data and 
> Address signal are synchronized. The problem is: 1) write/read signal 
> often generate one more period than what I needed. although I could 
> overcome it by adjust control signal's edge sensitivity, but it maybe 
> reappear when I resynthesize the design. The reason is time delay of 2 
> inputs(one is clock, one is control signal) of the LUT4 vary greatly. Can 
> I limit delay difference of the 2 inputs to an acceptable level? if it is, 
> How could I do? 2) the timing of address, data and write/read is 
> inconsistent with the timing required by ADI. I could delay some signal by 
> add buffers or invertors. But I am afraid if it is work well if I add this 
> modular to the top design. Is there any better way?
>
> if I generate the w/r signal synchronized with the clock, the problem may 
> do not exist. But I should drive the clock twice high, I don't know if 
> VirtexE can work well on 125MHz.
>
> Thank you for your advice. 

"Vladislav Muravin" <muravinv@advantech.ca> wrote in message
news:8Taee.12828$3U.745079@news20.bellglobal.com...
> (2) Just create an asynchronous interface, i.e. your "write" strobe is
your
> clock and the "read" strobe is the read clock.
> But this is more like spplication-specific, depends what exactly you'd
like
> to do.
>
You bad man! ;-) Personally, I'm against adding clocks wherever possible.
I'd much rather retime the data strobes into enables in a master clock
domain if it's at all possible. It's more work up front, but a lot easier
when you include the time taken to build your timing constraints in the UCF
file and debug the unsimulatable (!) timing errors that occur one in a
[m|b|tr]illion operations!.
YMMV, Syms.

Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface.

ADI chip use WR# signal as the write data latch, and RD# signal as read latch.

Write timing graph:

__________________ | Address | |_________________| | | |---8ns---| ______________ | | | Data | | | |____________| | | | | |3ns | | | | Write __________ _________ __| |________| |__ |--7ns---|

I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock.

The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level?

Thanks for your advice.

Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface.

ADI chip use WR# signal as the write data latch, and RD# signal as read latch.

Write timing graph:

__________________

| Address |

|_________________|

| |

|---8ns---| ______________

| | | Data |

| | |____________|

| | |

| |3ns |

| | |

Write

__________ _________

__| |________| |__

|--7ns---|

I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock.

The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level?

Thanks for your advice.

Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface.

ADI chip use WR# signal as the write data latch, and RD# signal as read latch.

Write timing graph:

__________________ | Address | |_________________| | | |---8ns---| ______________ | | | Data | | | |____________| | | | | |3ns | | | |

Write

__________ _________ __| |________| |__ |--7ns---|

I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock.

The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level?

Thanks for your advice.

Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface.

ADI chip use WR# signal as the write data latch, and RD# signal as read latch.

Write timing graph:

----------------- | Address | |----------------| | | |---8ns---| -------------- | | | Data | | | |------------| | | | | |3ns | | | |

Write

---------- --------- __| |________| |__ |--7ns---|

I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock.

The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level?

Thanks for your advice.

Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface.

ADI chip use WR# signal as the write data latch, and RD# signal as read latch.

Write timing graph:

-----------------

| Address |

|----------------|

| |

|---8ns---| --------------

| | | Data |

| | |------------|

| | |

| |3ns |

Write

---------- --------- __| |________| |__ |--7ns---|

I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock.

The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level?

Thanks for your advice.