Altera SDRam ip core

Hello,

I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM
Controller but it seems that there is something very wrong in what I
do.

When I send a write command to the controller, what I get on the
output using SignalTap is the write command issued to the SDRAM, but
only 2 clocks later come the data. So the first two word I read are
wrong, and the last two I write are lost.

I think the configuration of the controller and the sdram is right, it
runs at 50 MHz with a CAS of 2 (since it seems from the doc that the
controller cannot do 1)

If you have any idea ...

Thanks
Nick