Using capacitor to slow the rise time.

I know that we can vary the drive strength of the Virtex outputs and 
control the rise time. This just for my understanding of things.

Using a capacitor to ground to slow the rise time feels like a very 
wrong thing to do. But I am not able to convince others why its a bad 
practise?

The reasons I can come up with are
1) It increases the total current and hence can contribute to ground 
bounce and cross talk.
2) Total power dissipation in the device is increased.

3) It takes up board space, requires more components etc.(for now lets 
stick to the electrical aspect of things and ignore this issue)

I am unable convince that this practise is bad and a real issue.

Is there something I am missing?

Brijesh

Brijesh,

A cap directly at the output pin slows down the rise time, and is not 
all that bad.  I say that only because it sometimes has to be done.

It is a lot like a one-shot, you should be able to design everything 
without having to use one.

Or, like a "GO TO" statement in a program, something to avoid, as it is 
considered bad practice.

Placing the cap at the receiver is really bad from a signal integrity 
standpoint:  it makes for a huge reflection that may lead to 
discontinuities in the rising and falling edges.

(Much) Preferable to a cap load is to set the SLOW attribute, or use a 
weaker drive output.

Austin

Brijesh wrote:

> 
> I know that we can vary the drive strength of the Virtex outputs and 
> control the rise time. This just for my understanding of things.
> 
> Using a capacitor to ground to slow the rise time feels like a very 
> wrong thing to do. But I am not able to convince others why its a bad 
> practise?
> 
> The reasons I can come up with are
> 1) It increases the total current and hence can contribute to ground 
> bounce and cross talk.
> 2) Total power dissipation in the device is increased.
> 
> 3) It takes up board space, requires more components etc.(for now lets 
> stick to the electrical aspect of things and ignore this issue)
> 
> I am unable convince that this practise is bad and a real issue.
> 
> Is there something I am missing?
> 
> Brijesh

"Brijesh" <brijesh_xyz@cfrsi_xyz.com> wrote in message
news:d5g004$hui$1@solaris.cc.vt.edu...
>
> I know that we can vary the drive strength of the Virtex outputs and
> control the rise time. This just for my understanding of things.
>
> Using a capacitor to ground to slow the rise time feels like a very
> wrong thing to do. But I am not able to convince others why its a bad
> practise?
>
> The reasons I can come up with are
> 1) It increases the total current and hence can contribute to ground
> bounce and cross talk.
> 2) Total power dissipation in the device is increased.
>
> 3) It takes up board space, requires more components etc.(for now lets
> stick to the electrical aspect of things and ignore this issue)
>
> I am unable convince that this practise is bad and a real issue.
>
> Is there something I am missing?
>
> Brijesh

I haven't "gotten to a good place" yet with respect to slowing rise times
but I agree that adding capacitors to the output isn't an ideal solution.
What might work better (even more board space) is adding series resistors at
the drivers and capacitors on the other side of the resistor from the
driver.  The wave shape is less ideal, perhaps, but the high edge rate
transients traveling down the wire are significantly reduced without forcing
the high near-rail currents at the start of the transition.

For local point-to-point signals with a good ground reference, a series
resistor is still probably your best bet because you don't have many
mechanisms to be affected by high risetimes - EMI is still decent as long as
you don't switch routing planes far from a return path or cross plane
splits.

On Fri, 06 May 2005 10:50:54 -0400, Brijesh
<brijesh_xyz@cfrsi_xyz.com> wrote:

>
>I know that we can vary the drive strength of the Virtex outputs and 
>control the rise time. This just for my understanding of things.
>
>Using a capacitor to ground to slow the rise time feels like a very 
>wrong thing to do. But I am not able to convince others why its a bad 
>practise?
>
>The reasons I can come up with are
>1) It increases the total current and hence can contribute to ground 
>bounce and cross talk.
>2) Total power dissipation in the device is increased.
>
>3) It takes up board space, requires more components etc.(for now lets 
>stick to the electrical aspect of things and ignore this issue)
>
>I am unable convince that this practise is bad and a real issue.
>
>Is there something I am missing?
>
>Brijesh

I've avoided using capacitors on digital lines for the last 30 years.
Actually, that's not quite true.  About 10 years ago, another designer
I was working with convinced me that we had a special situation in
which a capacitor was called for.  So now my policy is, every 20 years
or so, go nuts.  Now that I think of it, I've also suggested using RCs
on I2C drivers that are too fast.  But that's about it.

And some folks might say that it's acceptable to filter
non-speed-critical digital signals that enter or leave a system, for
EMI purposes.  I haven't found it necessary, but I won't argue the
point. 

I avoid capacitors on digital lines because (1) the resulting risetime
is usually poorly controlled, (2) the resulting additional signal
delay is usually poorly controlled, (3) the capacitor is often used to
cover up an underlying design problem, e.g., a glitchy decoder driving
a synchronous input, and (4) I've always been able to find a better
solution.

I don't know how many people on this group read Joel Spolsky's "Joel
on Software" blog.  Spolsky has an interesting idea called the Joel
Test, a list of 12 questions with yes/no answers that you can use to
evaluate the quality of a software team.  You can find it here.

http://www.joelonsoftware.com/articles/fog0000000043.html

I think it would be an interesting idea to come up with a similar list
for digital hardware design.  And now Brijesh has provided me with the
inspiration to start such a list:

1) Do you use capacitors on digital lines?
2) Do you use analog one-shots in your designs?

A "yes" answer to either question should be accompanied by a whole lot
of 'splaining.

One other thought: CPLD and FPGA vendors did the digital design
community a great and lasting service by not including an "add a
capacitor to this net" feature.

Bob Perlman
Cambrian Design Works
  

Bob Perlman wrote:

>On Fri, 06 May 2005 10:50:54 -0400, Brijesh
><brijesh_xyz@cfrsi_xyz.com> wrote:
>
>  
>
>>I know that we can vary the drive strength of the Virtex outputs and 
>>control the rise time. This just for my understanding of things.
>>
>>Using a capacitor to ground to slow the rise time feels like a very 
>>wrong thing to do. But I am not able to convince others why its a bad 
>>practise?
>>
>>The reasons I can come up with are
>>1) It increases the total current and hence can contribute to ground 
>>bounce and cross talk.
>>2) Total power dissipation in the device is increased.
>>
>>3) It takes up board space, requires more components etc.(for now lets 
>>stick to the electrical aspect of things and ignore this issue)
>>
>>I am unable convince that this practise is bad and a real issue.
>>
>>Is there something I am missing?
>>
>>Brijesh
>>    
>>
>
>I've avoided using capacitors on digital lines for the last 30 years.
>Actually, that's not quite true.  About 10 years ago, another designer
>I was working with convinced me that we had a special situation in
>which a capacitor was called for.  So now my policy is, every 20 years
>or so, go nuts.  Now that I think of it, I've also suggested using RCs
>on I2C drivers that are too fast.  But that's about it.
>
>And some folks might say that it's acceptable to filter
>non-speed-critical digital signals that enter or leave a system, for
>EMI purposes.  I haven't found it necessary, but I won't argue the
>point. 
>
>I avoid capacitors on digital lines because (1) the resulting risetime
>is usually poorly controlled, (2) the resulting additional signal
>delay is usually poorly controlled, (3) the capacitor is often used to
>cover up an underlying design problem, e.g., a glitchy decoder driving
>a synchronous input, and (4) I've always been able to find a better
>solution.
>
>I don't know how many people on this group read Joel Spolsky's "Joel
>on Software" blog.  Spolsky has an interesting idea called the Joel
>Test, a list of 12 questions with yes/no answers that you can use to
>evaluate the quality of a software team.  You can find it here.
>
>http://www.joelonsoftware.com/articles/fog0000000043.html
>
>I think it would be an interesting idea to come up with a similar list
>for digital hardware design.  And now Brijesh has provided me with the
>inspiration to start such a list:
>
>1) Do you use capacitors on digital lines?
>2) Do you use analog one-shots in your designs?
>  
>
    3) do you connect logic outputs to clock inputs (or do you use gated 
clocks)?
  
   

>A "yes" answer to either question should be accompanied by a whole lot
>of 'splaining.
>
>One other thought: CPLD and FPGA vendors did the digital design
>community a great and lasting service by not including an "add a
>capacitor to this net" feature.
>
>Bob Perlman
>Cambrian Design Works
>  
>
>
>
>
>  
>


-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

"Ray Andraka" <ray@andraka.com> wrote in message
news:iHOee.5377$aB.4807@lakeread03...
> Bob Perlman wrote:
>
> >
> >1) Do you use capacitors on digital lines?
> >2) Do you use analog one-shots in your designs?
> >
> >
>     3) do you connect logic outputs to clock inputs (or do you use gated
> clocks)?
>
>
4) Have you had any bugs that 'fixed themselves' without you knowing why?
(They always come back!)
5) Any unterminated digital lines going off board and/or longer than c.15cm?

Cheers, Syms.

Symon wrote:

> "Ray Andraka" <ray@andraka.com> wrote in message
> news:iHOee.5377$aB.4807@lakeread03...
> 
>>Bob Perlman wrote:
>>
>>
>>>1) Do you use capacitors on digital lines?
>>>2) Do you use analog one-shots in your designs?
>>>
>>>
>>
>>    3) do you connect logic outputs to clock inputs (or do you use gated
>>clocks)?
>>
>>
> 
> 4) Have you had any bugs that 'fixed themselves' without you knowing why?
> (They always come back!)
> 5) Any unterminated digital lines going off board and/or longer than c.15cm?

Iam not aware what c.15cm means?

Guess what we already have 32 bit bus which is going off board without 
any termination on the board. The reasoning was "its a slow bus we are 
only going to operate it at xMHz". The layout was originally intended to 
be used as LVDS bus and had termination for LVDS. But now its being used 
as LVTTL outputs over 6ft SCSI cable. I just lowered the drive strength 
  to 4mA and crossed my fingers. :-) Worst part is it is working, making 
me wonder if I am the one who is paranoid?

I have observed that even though people have read and know that its the 
rise time that matters. They still tend to think like "its only 4MHz, 
termination is not a issue". I think we have already been burnt by this 
in a differnt project. Solution that is being adapted is to slow the 
signal by putting a capacitor instead of treating the signal with care 
in layout and termination. (Iam talking about serial clk out of the FPGA 
in master serial programming mode)

Ray, I think you know what I am talking about :-).

These question are really helpful for the new engineers like me. Hope 
more people will contribute. :-)

Brijesh

> 
> Cheers, Syms.
> 
> 

>Bob Perlman wrote:
>1) Do you use capacitors on digital lines?
>2) Do you use analog one-shots in your designs?

>Ray Andraka wrote:
>3) do you connect logic outputs to clock inputs (or do you use gated
>   clocks)?

>Symon Brewer wrote:
>4) Have you had any bugs that 'fixed themselves' without you knowing why?
>   (They always come back!)
>5) Any unterminated digital lines going off board and/or longer than c.15cm?

>Philip Freidin wrote:
>6) Do you have any pet theories on how to fix metastables?
>
>7) Do you use the async set and reset pins on FFs for other than
>   system initialization?

Philip Freidin wrote:

>>Bob Perlman wrote:
>>1) Do you use capacitors on digital lines?
>>2) Do you use analog one-shots in your designs?
>>    
>>
>
>  
>
>>Ray Andraka wrote:
>>3) do you connect logic outputs to clock inputs (or do you use gated
>>  clocks)?
>>    
>>
>
>  
>
>>Symon Brewer wrote:
>>4) Have you had any bugs that 'fixed themselves' without you knowing why?
>>  (They always come back!)
>>5) Any unterminated digital lines going off board and/or longer than c.15cm?
>>    
>>
>
>  
>
>>Philip Freidin wrote:
>>6) Do you have any pet theories on how to fix metastables?
>>
>>7) Do you use the async set and reset pins on FFs for other than
>>  system initialization?
>>    
>>
>
>
>
>  
>
8) Do you use pull up resistors on fast CMOS busses that require less 
than 10ns/V rise / fall time?

Brijesh wrote:
> 
> I know that we can vary the drive strength of the Virtex outputs and 
> control the rise time. This just for my understanding of things.
> 
> Using a capacitor to ground to slow the rise time feels like a very 
> wrong thing to do. But I am not able to convince others why its a bad 
> practise?
> 
> 

It's bad in practice -- however to slow the rise & fall time of an edge 
one can accomplish this a number of ways -- I assume you need to slow 
the edge down (irrespective of the signal frequency 100Khz vs 100Mhz) is 
that you are noticing some Signal Integrity issues such as reflections 
or crosstalk. If so the real answer would be to terminate your 
transmission properly to eliminate any SI issues with your fast driver. 
See Howard Johnson's (Black Magic) book on SI or visit IDT, TI or other 
IC manufacturers website and look for the app notes on SI, ground 
bounce, crosstalk etc... they have some nice primers on SI.

Too slow edges down - use source series terminators, an RC filter at the 
source, a source series resistor with a PI filter, ferrite bead, adjust 
the slew of the driver in the FPGA, choose a slower IO standard in the 
FPGA, so on and so forth ...

Good luck ....

JoeG