Bob Perlman schrieb:> I avoid capacitors on digital lines because [...] (3) the capacitor is often used to > cover up an underlying design problem,<rant> You mean like in this design: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html Were they put in capacitors behind the drivers to cover up a race condition in the programmer software? </rant> Kolja Sulimma
Using capacitor to slow the rise time.
Started by ●May 6, 2005
Reply by ●May 7, 20052005-05-07
Reply by ●May 7, 20052005-05-07
>>> Bob Perlman wrote: >>> 1) Do you use capacitors on digital lines? >>> 2) Do you use analog one-shots in your designs? >>> >>> Ray Andraka wrote: >>> 3) do you connect logic outputs to clock inputs (or do you use gated >>> clocks)? >>> >>> Symon Brewer wrote: >>> 4) Have you had any bugs that 'fixed themselves' without you knowing >>> why? >>> (They always come back!) >>> 5) Any unterminated digital lines going off board and/or longer than >>> c.15cm? >>> >>> Philip Freidin wrote: >>> 6) Do you have any pet theories on how to fix metastables? >>> >>> 7) Do you use the async set and reset pins on FFs for other than >>> system initialization? >>>Thomas Rudloff wrote:>> > 8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time?9) In what situations might it be acceptable knowingly violate worst case timing specs?
Reply by ●May 7, 20052005-05-07
On Sat, 07 May 2005 16:05:13 GMT, Jeff Cunningham <jcc@sover.net> wrote:>>>> Bob Perlman wrote: >>>> 1) Do you use capacitors on digital lines? >>>> 2) Do you use analog one-shots in your designs? >>>> >>>> Ray Andraka wrote: >>>> 3) do you connect logic outputs to clock inputs (or do you use gated >>>> clocks)? >>>> >>>> Symon Brewer wrote: >>>> 4) Have you had any bugs that 'fixed themselves' without you knowing >>>> why? >>>> (They always come back!) >>>> 5) Any unterminated digital lines going off board and/or longer than >>>> c.15cm? >>>> >>>> Philip Freidin wrote: >>>> 6) Do you have any pet theories on how to fix metastables? >>>> >>>> 7) Do you use the async set and reset pins on FFs for other than >>>> system initialization? >>>> >Thomas Rudloff wrote: >>> >> 8) Do you use pull up resistors on fast CMOS busses that require less >> than 10ns/V rise / fall time? > >9) In what situations might it be acceptable knowingly violate worst >case timing specs?Good question, Jeff, but we're looking for questions with yes/no answers. Bob Perlman Cambrian Design Works
Reply by ●May 8, 20052005-05-08
Bob Perlman wrote:> On Sat, 07 May 2005 16:05:13 GMT, Jeff Cunningham <jcc@sover.net> > wrote: > > >>>>>Bob Perlman wrote: >>>>>1) Do you use capacitors on digital lines? >>>>>2) Do you use analog one-shots in your designs? >>>>> >>>>>Ray Andraka wrote: >>>>>3) do you connect logic outputs to clock inputs (or do you use gated >>>>> clocks)? >>>>> >>>>>Symon Brewer wrote: >>>>>4) Have you had any bugs that 'fixed themselves' without you knowing >>>>>why? >>>>> (They always come back!) >>>>>5) Any unterminated digital lines going off board and/or longer than >>>>>c.15cm? >>>>> >>>>>Philip Freidin wrote: >>>>>6) Do you have any pet theories on how to fix metastables? >>>>> >>>>>7) Do you use the async set and reset pins on FFs for other than >>>>> system initialization? >>>>> >> >>Thomas Rudloff wrote: >> >>>8) Do you use pull up resistors on fast CMOS busses that require less >>>than 10ns/V rise / fall time? >> >>9) In what situations might it be acceptable knowingly violate worst >>case timing specs? > > > Good question, Jeff, but we're looking for questions with yes/no > answers. > > Bob Perlman > Cambrian Design WorksLet me rephrase: 9) Do you ever knowingly violate worst case timing specs?
Reply by ●May 8, 20052005-05-08
>Bob Perlman wrote: >1) Do you use capacitors on digital lines? >2) Do you use analog one-shots in your designs? > >Ray Andraka wrote: >3) Do you connect logic outputs to clock inputs (or do you use gated > clocks)? > >Symon Brewer wrote: >4) Have you had any bugs that 'fixed themselves' without you knowing > why? (They always come back!) >5) Any unterminated digital lines going off board and/or longer than > c.15cm? > >Philip Freidin wrote: >6) Do you have any pet theories on how to fix metastables? > >7) Do you use the async set and reset pins on FFs for other than > system initialization? > >Thomas Rudloff wrote: >8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time? > >Jeff Cunningham wrote: >9) Do you ever knowingly violate worst case timing specs? > > >Philip Freidin wrote (again): >10) Do you only use time specs for the "important" parts of your design?Philip Freidin Fliptronics
Reply by ●May 9, 20052005-05-09
> 8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time?I dont know the answer to this question. Never worked with CMOS devices. Does it have anything to do with the fact that CMOS has lower rise time than fall time? In our VLSI class projects when were building the CMOS gates we would always make the P type gate twice as large as N type just to take care of this issue. Brijesh
Reply by ●May 11, 20052005-05-11
Bob Perlman wrote:> On Sat, 07 May 2005 16:05:13 GMT, Jeff Cunningham <jcc@sover.net> > wrote: > > >>>>>Bob Perlman wrote: >>>>>1) Do you use capacitors on digital lines? >>>>>2) Do you use analog one-shots in your designs? >>>>> >>>>>Ray Andraka wrote: >>>>>3) do you connect logic outputs to clock inputs (or do you use gated >>>>> clocks)? >>>>> >>>>>Symon Brewer wrote: >>>>>4) Have you had any bugs that 'fixed themselves' without you knowing >>>>>why? >>>>> (They always come back!) >>>>>5) Any unterminated digital lines going off board and/or longer than >>>>>c.15cm? >>>>> >>>>>Philip Freidin wrote: >>>>>6) Do you have any pet theories on how to fix metastables? >>>>> >>>>>7) Do you use the async set and reset pins on FFs for other than >>>>> system initialization? >>>>> >> >>Thomas Rudloff wrote: >> >>>8) Do you use pull up resistors on fast CMOS busses that require less >>>than 10ns/V rise / fall time? >> >>9) In what situations might it be acceptable knowingly violate worst >>case timing specs?10) Do you ever use LUTs as delay elements to change interface timings? Jeremy
Reply by ●May 11, 20052005-05-11
Philip Freidin wrote:>Bob Perlman wrote: >1) Do you use capacitors on digital lines? >2) Do you use analog one-shots in your designs? > >Ray Andraka wrote: >3) Do you connect logic outputs to clock inputs (or do you use gated > clocks)? > >Symon Brewer wrote: >4) Have you had any bugs that 'fixed themselves' without you knowing > why? (They always come back!) >5) Any unterminated digital lines going off board and/or longer than > c.15cm? > >Philip Freidin wrote: >6) Do you have any pet theories on how to fix metastables? > >7) Do you use the async set and reset pins on FFs for other than > system initialization? > >Thomas Rudloff wrote: >8) Do you use pull up resistors on fast CMOS busses that require less > than 10ns/V rise / fall time? > >Jeff Cunningham wrote: >9) Do you ever knowingly violate worst case timing specs? > > >Philip Freidin wrote (again): >10) Do you only use time specs for the "important" parts of your design? >>Jeremy Stringer wrote (again): >11) Do you ever use LUTs as delay elements to change interface timings?
