"Mine is bigger than yours..."

It's again time for the annual bragging frenzy, where every FPGA
manufacturer claims to have the biggest.

It seems so simple:
The Xilinx XC4VLX200 has 178,176 LUTs + associated flip-flops,
while the Altera EP2S180 has 143,520 ALUTs + flip-flops.
The conclusion is obvious, isn't it?

But this is not that simple. In the world of creative marketing,
everyone can claim to be the winner.

First Xilinx muddies the water by adding 12.5% to the LUT count, to get
credit for various embellishments, bringing the XC4VLX200 to 200,448
"Logic Cells". Crashing through the 200 000 barrier...

But Altera cannot stand to be left behind. They get creative and apply
a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576
"equivalent LUTs", thus even bigger than the Xilinx behemoth.
Altera also claims superiority in multipliers and RAM bits, but forgets
that the cheaper XC4VSX55 or XC4FX140 are much better endowed with
those attributes.

It is so easy to ridicule this puerile bragging contest and its
Freudian fix on one specific aspect, while ignoring far more important
features. Unfortunately, some poor innocent person might actually get
fooled by it.   Too bad!

For a more entertaining story, click on
http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm

Peter Alfke, Xilinx Applications

Peter Alfke wrote:

> It is so easy to ridicule this puerile bragging contest and its
> Freudian fix on one specific aspect, while ignoring far more important
> features. Unfortunately, some poor innocent person might actually get
> fooled by it.   Too bad!

One way to avoid being fooled is
to write portable code and run
a trial synthesis/route/STA
for all the contesting devices.


         -- Mike Treseler

Peter Alfke wrote:
> 
> It's again time for the annual bragging frenzy, where every FPGA
> manufacturer claims to have the biggest.
> 
> It seems so simple:
> The Xilinx XC4VLX200 has 178,176 LUTs + associated flip-flops,
> while the Altera EP2S180 has 143,520 ALUTs + flip-flops.
> The conclusion is obvious, isn't it?

...

> It is so easy to ridicule this puerile bragging contest and its
> Freudian fix on one specific aspect, while ignoring far more important
> features. Unfortunately, some poor innocent person might actually get
> fooled by it.   Too bad!
> 
> For a more entertaining story, click on
> http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm
> 
> Peter Alfke, Xilinx Applications


Indeed a nice Article !

I feel it failed to address two important points that I, as a
customer, also find very important:

1) When I send en email to a company that will be deeply involved
in my revenue stream as a supplier of parts and tools, I expect
them to be responsive. Every time I send an email to Xilinx
(regardless if it is sales, tech support, or marketing) I get a
reply within 24 hours (we are in a different time zone as well +9h).
Out of the dozen or so emails we sent to Altera in the last year++
exactly zero where replied to (we either lost the customers who
asked for Altera based solutions, or where able to convert them
to Xilxinx based solutions). To bad !

2) Look at this newsgroup. Peter and Austin are always there in
the front line, standing up for their company, taking the heat
and bs from an open public forum. Plus Xilinx makes it a point
to have additional experts peeking in the group and helping
out where needed. Any problem reported is discussed in the open
and solved. There is no under the rug filing or shutting up the
customers. I can download an errata or post to the newsgroup
and get open solutions. I can't say that I see a lot of that
from Altera. Yes Paul seems to be out there as well, taking on
a fight here and there. But I find there is a lack of discussion
level as with Xilinx. I know if I run in to a problem with Xilinx
devices, I can always turn to this news group and get help.

Just my two Euro-cent ...

Best Regards, 
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

The conclusion clearly isn't obvious. Designs are not flip-flop
limited so counting flip-flops and assuming this somehow equates to a
customer experience is rather naive (though certainly convenient for an
architecture that isn't optimized for logic efficiency). Altera has
used our entire benchmark suite to validate the facts.

Realistically of course customers should check out their own designs.
No customer will ever find a real design that lines up with the 30%
larger Xilinx claim (comparing the biggest devices). Most will find the
2S180 a little larger than the LX200 based on logic and a whole lot
larger based on RAM and DSP resources.

And customers should also try to actually purchase these large devices
before making any decisions. Unfortunately the "vast" 90 nm
experience making small density Spartan-3 devices doesn't translate
to actually shipping high-density parts. While there are likely a few
LX200 or LX160 devices that have shipped, facts are that Altera sales
are greater on the 2S130 and 2S180 devices alone than the collective
sales of all Virtex-4 products. Altera's patented redundancy,
operational excellence, and strategy of sticking to a single fab
partner significantly reduce risk for customers who need guaranteed
delivery of high-density FPGAs.

Dave Greenfield
Altera Marketing

> Peter Alfke wrote:
>
> > It is so easy to ridicule this puerile bragging contest and its
> > Freudian fix on one specific aspect, while ignoring far more
important
> > features. Unfortunately, some poor innocent person might actually
get
> > fooled by it.   Too bad!
>

>One way to avoid being fooled is
>to write portable code and run
>a trial synthesis/route/STA
>for all the contesting devices.

Does anybody have any data on how much performance (space or time) you
can gain by hacking some nice pretty portable code to take advantage
of device specific features?

How much time does it take to "try it" if that includes a round
of manual placement?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

Hi Peter,

> It is so easy to ridicule this puerile bragging contest and its
> Freudian fix on one specific aspect, while ignoring far more important
> features. Unfortunately, some poor innocent person might actually get
> fooled by it.   Too bad!

Yep. In The Netherlands we call it a far-peeing contest.

However, I have been subjected to a customer who made a vendor decision for
a low-cost device based on the fact that this vendor at the time also
happened to have the largest high-end FPGA in the market. I kid you not.
Took me two days to regain my confidence in humanity. If this happens in a
postage-size country like The Netherlands, it must happen in other places -
we're not _that_ much more unreasonable than other countries...

> For a more entertaining story, click on
> http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm

Wonderful! Thanks for the link!

Ben

I did a correlator for Stratix with 8 parallel MACs where the 2nd try
was better than the 1st by 3x fewer logic cells and 50% better fmax,
just by moving the accumulators and moving (not adding) pipelining.
That's probably pretty extreme, but without taking a close look at the
Stratix DSP block I don't think I would have realized it.

Depending on how you code barrel shifters on Stratix II you can get big
savings by using the ALM to its maximum capability. I'd love to find
lots of other functions that map really well into the ALM.

-- Pete


> Does anybody have any data on how much performance (space or time)
you
> can gain by hacking some nice pretty portable code to take advantage
> of device specific features?
>
> How much time does it take to "try it" if that includes a round
> of manual placement?
>
> --
> The suespammers.org mail server is located in California.  So are all
my
> other mailboxes.  Please do not send unsolicited bulk e-mail or
unsolicited
> commercial e-mail to my suespammers.org address or any of my other
addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.

> 2) Look at this newsgroup. Peter and Austin are always there in
> the front line, standing up for their company, taking the heat
> and bs from an open public forum. Plus Xilinx makes it a point
> to have additional experts peeking in the group and helping
> out where needed. Any problem reported is discussed in the open
> and solved. There is no under the rug filing or shutting up the
> customers. I can download an errata or post to the newsgroup
> and get open solutions. I can't say that I see a lot of that
> from Altera. Yes Paul seems to be out there as well, taking on
> a fight here and there. But I find there is a lack of discussion
> level as with Xilinx. I know if I run in to a problem with Xilinx
> devices, I can always turn to this news group and get help.

Rudi,

I don't think this point is quite fair. Besides Paul there are myself
(Nios/embedded questions here are what I answer), Vaughn, and others.
On the embedded side a lot of people have moved over to asking
questions on a new webaite (www.niosforum.com) where there area Altera
people from the engineering/apps/marketing teams who respond quite
regularly.

I won't comment on the original FPGA Journal article, other than to say
that I enjoyed it :) On the other hand, one should realize that X has
been playing the same marketing games for years now without a peep from
the press...

Jesse Kempa
Altera

I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's
more) have responded quickly to things with Nios, Quartus, etc, from my
point of view. Take a look at how often, ie., Subrotto has responded to
problem designs in the past. I'm very thankful for their presence.

As for getting to people inside Altera, develop a good relationship
with the FAE and let them do that for you - it's worked for me.

-- Pete

> Rudi,
>
> I don't think this point is quite fair. Besides Paul there are myself
> (Nios/embedded questions here are what I answer), Vaughn, and others.
> On the embedded side a lot of people have moved over to asking
> questions on a new webaite (www.niosforum.com) where there area
Altera
> people from the engineering/apps/marketing teams who respond quite
> regularly.
>
> I won't comment on the original FPGA Journal article, other than to
say
> that I enjoyed it :) On the other hand, one should realize that X has
> been playing the same marketing games for years now without a peep
from
> the press...
> 
> Jesse Kempa
> Altera

Peter Sommerfeld wrote:

> I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's
> more) have responded quickly to things with Nios, Quartus, etc, from my
> point of view. Take a look at how often, ie., Subrotto has responded to
> problem designs in the past. I'm very thankful for their presence.
> 
> As for getting to people inside Altera, develop a good relationship
> with the FAE and let them do that for you - it's worked for me.
> 
> -- Pete
> 
>> Rudi,
>>
>> I don't think this point is quite fair. Besides Paul there are myself
>> (Nios/embedded questions here are what I answer), Vaughn, and others.
>> On the embedded side a lot of people have moved over to asking
>> questions on a new webaite (www.niosforum.com) where there area
> Altera
>> people from the engineering/apps/marketing teams who respond quite
>> regularly.
>>
>> I won't comment on the original FPGA Journal article, other than to
> say
>> that I enjoyed it :) On the other hand, one should realize that X has
>> been playing the same marketing games for years now without a peep
> from
>> the press...
>> 
>> Jesse Kempa
>> Altera



Jesse, Pete,

I did not intend to offend anybody. I am sure there are many
great guys here from both camps. My point was that I seem more
tough discussions in the Xilinx camp.

I don't know what the cause for that is. Are Altera user not
doing any (b)leading edge designs ? Are they not using any
fancy features of the devices, are they not pushing the devices
to the limit ? I don't know. It's just my personal observation ...

Regards,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis