"Mine is bigger than yours..."

On Fri, 13 May 2005 13:10:33 +0700, Rudolf Usselmann wrote:

> Peter Sommerfeld wrote:
> 
>> I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's
>> more) have responded quickly to things with Nios, Quartus, etc, from my
>> point of view. Take a look at how often, ie., Subrotto has responded to
>> problem designs in the past. I'm very thankful for their presence.
>> 
>> As for getting to people inside Altera, develop a good relationship
>> with the FAE and let them do that for you - it's worked for me.
>> 
>> -- Pete
>> 
>>> Rudi,
>>>
>>> I don't think this point is quite fair. Besides Paul there are myself
>>> (Nios/embedded questions here are what I answer), Vaughn, and others.
>>> On the embedded side a lot of people have moved over to asking
>>> questions on a new webaite (www.niosforum.com) where there area
>> Altera
>>> people from the engineering/apps/marketing teams who respond quite
>>> regularly.
>>>
>>> I won't comment on the original FPGA Journal article, other than to
>> say
>>> that I enjoyed it :) On the other hand, one should realize that X has
>>> been playing the same marketing games for years now without a peep
>> from
>>> the press...
>>> 
>>> Jesse Kempa
>>> Altera
> 
> 
> 
> Jesse, Pete,
> 
> I did not intend to offend anybody. I am sure there are many
> great guys here from both camps. My point was that I seem more
> tough discussions in the Xilinx camp.
> 
> I don't know what the cause for that is. Are Altera user not
> doing any (b)leading edge designs ? Are they not using any
> fancy features of the devices, are they not pushing the devices
> to the limit ? I don't know. It's just my personal observation ...
> 
> Regards,
> rudi

It might also be at least partly to do with the type of people
representing Xilinx and Altera in this newsgroup.  I get the impression
that certain Xilinx posters provoke discussions and arguements by their
enthusiastic or agressive (depending on your viewpoint) promotion of
Xilinx parts, while most Altera posters seem quieter, and will answer when
asked.  Both camps appear to have knowledgable and helpful posters,
although obviously you have to remember that sometimes their facts and
figures are seen from a biased viewpoint.

Having not used Xilinx devices, I've had no occasion to test Xilinx
support - but when I asked for help here for Altera devices, I got general
information here, more specific help in private emails, contact from my
FAE (obviously Altera people work closely with their FAEs), and in general
a lot of interesting and useful information.  The problem turned out to be
a typo in my code with bizarre side effects, but I was very happy with the
support I got.

Rudi,

No offense taken at all. If you have any sort of Altera question you
think is suitable for the news group, feel free to ask here and I'd say
there is a good likelihood of it getting answered. I think David's
comment below reflects the personalities of the individuals from A & X
who post here pretty accurately.

On your other question about leading edge designs - the people who will
see this each day are the sales/FAE staff for each company. My
intuition and customer experience tells me that the competition is
fierce and both companies' products are used in leading edge designs in
all sorts of markets, but any more (from me) would be pure speculation.

Jesse Kempa
Altera

"Rudolf Usselmann" <russelmann@hotmail.com> schrieb im Newsbeitrag
news:d61gcq$qu0$1@nobel.pacific.net.sg...
> Peter Sommerfeld wrote:
>
[snip]

> Jesse, Pete,
>
> I did not intend to offend anybody. I am sure there are many
> great guys here from both camps. My point was that I seem more
> tough discussions in the Xilinx camp.
>
> I don't know what the cause for that is. Are Altera user not
> doing any (b)leading edge designs ? Are they not using any
> fancy features of the devices, are they not pushing the devices
> to the limit ? I don't know. It's just my personal observation ...
>
> Regards,
> rudi

Hi Rudi,

there defenetly are bleading edge designg on Altera devices.
what might interest you is that the only really available low cost ($795)
FPGA PCIe board is based on Altera and not on Xilinx silicon.
Altera also claims that the Stratix-GX based PCIe solution passed
compliance testing in full. Thats of course BS as the Stratix-GX
has about the same amount of PCIe compliance issues as rocketIO/X (pre V4)
but the Stratix-GX can pass PCIe compliance on the PCIe plugfest even
if it is not fully compliant to the PCIe spec (those non compliance issues
dont actually matter in most real life applications). And as it has been
said here the new GX FPGA is coming too...

Antti

Hi Ben,

Some 'real world' comments:
I think it's stuck in human nature to compare, therefore 'mine is
bigger than yours' has nothing to do with programmable logic at all.
Have you ever seen an customer that needs 'all' the features even if
this feature happens to be 'the biggest device'? Of course there will
be some customers spending 1000's of dollars on research projects, but
I guess your boss will like it more that you spend your time with the
customers that need lot's of FPGA's!
Any idea what percentage of the revenue these high gate count devices
represent? I guess something like 1%. So spending lot's of R&D money
on those devices isn't worth it. That's reality I'm afraid.

Luc

On Thu, 12 May 2005 20:53:29 GMT, Ben Twijnstra <btwijnstra@gmail.com>
wrote:

>Hi Peter,
>
>> It is so easy to ridicule this puerile bragging contest and its
>> Freudian fix on one specific aspect, while ignoring far more important
>> features. Unfortunately, some poor innocent person might actually get
>> fooled by it.   Too bad!
>
>Yep. In The Netherlands we call it a far-peeing contest.
>
>However, I have been subjected to a customer who made a vendor decision for
>a low-cost device based on the fact that this vendor at the time also
>happened to have the largest high-end FPGA in the market. I kid you not.
>Took me two days to regain my confidence in humanity. If this happens in a
>postage-size country like The Netherlands, it must happen in other places -
>we're not _that_ much more unreasonable than other countries...
>
>> For a more entertaining story, click on
>> http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm
>
>Wonderful! Thanks for the link!
>
>Ben

I've had a similar experience with a V4sx55 design.  Trying to 
synthesize from RTL code and achieve high performance takes a lot of 
"pushing on a rope", is frequently broken by gratuitous changes in the 
synthesis algorithm from version to version, and then often won't meet 
timing without a heroic placement effort.  doing structural 
instantiation gets me the performance in less overall time, but at the 
price of a design that is not very portable.



-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

kempaj@yahoo.com wrote:

> I don't think this point is quite fair.

Well, IMHO it is quite fair. The quality of support from
the Xilinx-associated experts is far better than from Altera.
A striking example: once I asked here about clocking
of the Cyclone 1C6 device (i.e. is it possible to use 
a sine wave as a clock source of a PLL?). And it was
a Xilinx guy who gave me a comprehensive answer... :-)

    Best regards
    Piotr Wyderski

Past:  I did a lot of leading edge (in terms of size) FPGA designs for
ASIC prototyping.   Size, usability, and cycle-time is of the essense.
In the past, I have used Orca (1996), Virtex , VirtexE,  and V2.  About
5 years ago, I looked at Altera and Quartus pretty much shot them in
the foot.

Current: In the new design, I once again evaluated state of the art
FPGAs.  For this cycle Virtex4's timeline was a little too late (by a
couple of months), so I started in StratixII (2S130s and 2S180s).  So
far, I have been very impressed with the tools and results.

Note: Altera's FPGA is not totally symmetric.  Different types of
memory, different type of PLLs, only certain PLLs can do feedback,
vertical I/Os are different than horizontal I/Os.  I thought this would
be difficult to keep straight.  However, I am getting to realize the
design I am working on is very not symmetric, so this has not been a
problem.

Memory:  I first thought that having to worry about the different types
of memory (512, 4K, 512K) was going to cause a accounting nightmare,
but you can actually set it to decide for you.   Quartus decides for
itself which one to use.  I really like this.

Synthesis: I have been impressed with the synthesis results.  Not as
good as Synplify Pro, but it comes with Quartus II.  We are having a
problem where Synplify is not finishing on one of the FPGAs and having
the Quartus synthesis engine saved us.  Also, synthesis in Quartus
takes about 2x-3x more computer time than synthesis in Synplify.

Physical Synthesis:  I was incredibly impressed with this since it is a
check box (vs. psuedo-floorplanning with Amplify or hand modification
with Precision).  For me, it is the difference between closing and not
closing timing.  One note though, some of my design grow by 20% when I
turn this on, so make sure you have a lot of head room.

Logic: I really like the ALM.  It does cut down on the number of levels
the logic has to go through.  This helps with timing.  Despite what
either Altera or Xilinx have to say, I really don't need a 1:1 ratio of
logic elements to FF.  About 10:1 ratio for ASIC prototyping is a
better ratio.  I would really like to see what other designers see.  I
would really like to see future families have at least 2x more logic
vs. FFs.

PLLs:  I like the analog PLLs vs. DPLLs of Xilinx.  One warning, if you
set QuartusII to decide the PLL type, you may not get to use all the
ratios.  Kind of bizarre, but that is the way I interpreted the tool.
I just set to only use Enhanced and the problem went away.

General: The tool flow is a little bit cleaner, but the Xilinx tool
flow was pretty good, so that is a wash.  I am not a tcl expert, so it
takes a little getting used to.  I do like when you finally get all the
tcl scripts right, you don't have to remember any switches, but once
again a wash.

Support: I am getting great support both locally and from the factory.
Of course your mileage will vary and may ultimately determine your
choice and your success.

Not used: I did not use processors, high speed transceivers, other IOs.


Cons 1: I was playing around with some different partition and I had a
design that was 85% full (in terms of logic) and Quartus II could no
route it at all (with no timing constraints).  To be fair, I have other
partitions with more than 90% that did route.  In previous Xilinx
devices in the Virtex* family, I only had problems closing time (i.e.
routing did not fail) at 95%, so budget your size appropriately.

Cons 2: Currently, there is no flash part that could program more than
1 of these large devices.  It really makes the JTAG chain on the board
needlessly complicated.

-Edwin

Hi Peter,

> But Altera cannot stand to be left behind. They get creative and apply
> a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576
> "equivalent LUTs", thus even bigger than the Xilinx behemoth.

I believe that there is a fair bit of literature explaining where the 
multiplier comes from.  Perhaps you (and others) do not believe the Stratix 
II vs. Virtex-4 comparison.  However, we also have data on Stratix II vs. 
Stratix utilizaiton showing ~25% higher utilization than you would expect 
from straight LUT/FF counting.  I certainly hope we are capable of measuring 
our own chips.  And previous (Altera-published) results showed that Stratix 
I achieves a higher logic density than Virtex-2.   So the 1.3 multiplier is 
at least consistant with other results.

Here is a link to a white-paper comparing Stratix II and Virtex-4 logic 
densities.  http://www.altera.com/literature/wp/wpstxiixlnx.pdf.  And here 
is another white paper on the ALM 
http://www.altera.com/literature/wp/wpstxiiple.pdf.

There are also two academic papers published in respected, referred FPGA 
conferences.  Both are authored by individuals who have established 
reputations in the FPGA industry.  The first paper describes the Stratix II 
architecture, including a section on the ALM (Lewis et al, "The Stratix II 
logic and routing architecture", Proceedings of the 2005 ACM/SIGDA 13th 
international symposium on FPGAs --  
http://www.eecg.toronto.edu/~jayar/pubs/lewis/lewisfpga05.pdf).  The second 
is specifically on the ALM (M. Hutton et al, "Improving FPGA performance and 
area using an adaptive logic module", International Conference on 
Field-Programmable Logic and Applications 2004).

The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs (like 
a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, and other 
more powerful combinations (such as 2 6-LUTs that share 4 inputs, etc). 
When you technology map a design into a specific look-up table (LUT) size, 
you get a variety of LUT sizes -- you can't map all the logic to use exactly 
4-inputs (for example).  Since you have a distribution of LUT sizes, the 
capability to pair more than just 2 4-LUTs into a single ALM will result in 
a decrease in the number of ALMs required.

Regards,

Paul Leventis
Altera Corp.

P.S. Ours is bigger -- and we can use it better too! 

Here is one more opinion from a person that only does FPGAs from time to 
time. I guess that makes me a non-professional :) (The rest of the work 
time is spent doing hardware design and writing code.)

Long time ago I was impressed by the Altera tools when I needed to do  a 
simple CPLD, but found out that the A parts were much more difficult to 
get than X parts. So I ended up using 95xx. Mostly for this historic 
reason when it came to finding cheap FPGAs I have looked at the
Spartan 2/3 line first. The free picoblaze was a big bonus too.
Then I had to do another desing on a Cyclone and took another look at 
the A tools. A number of pleasant surprises. I wish the two giants would 
take the best features from the other one! So here is my list of great 
thing in one that is not in the other in no particular order.

1. Quartus has a fantastic tool to do both built-in logic analysis and 
modify the BRAM on the fly. ChipScope appears to be harder to use unless 
I'm missing something. For example it won't work unless all the inputs 
are connected to valid signals. No way to have spare inputs and do late 
routing. No way to read/write BRAM unless you write a JTAG utility 
yourself. Big plus to A.

2. Neat table view of the build results all in one place.
3. Timing results easier to track.

On the other hand:

1. No free CPU. Had to make my own: Nios may be great but one hell of an 
overkill for my project.
2. Not enough BRAM in Cyclone. Does the Cyclone 2 exist outside the lab yet?
3. Very few development boards with A chips.

So that project done I'm mostly back in the X camp. Wish they could add 
the memory access tool...

Hi Alex,

Glad to hear you had a (mostly) postive Altera experience.  I've sent your 
feedback on to the planning folks.  And if you need a CPLD in the future, 
take a peak at Max II.

> 2. Not enough BRAM in Cyclone. Does the Cyclone 2 exist outside the lab 
> yet?

Yes, Cyclone II is available.  The EP2C35 is shipping and the EP2C70 and 
EP2C20 will be shipping very soon (May and June respectively according to 
http://www.altera.com/products/devices/cyclone2/overview/cy2-overview.html). 
The product roll-out is going very well and devices are rolling out ahead of 
schedule.

Regards,

Paul Leventis
Altera Corp.