"Mine is bigger than yours..."

"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message 
news:PaudnRAmKPtWBhTfRVn-vA@rogers.com...
> Hi Peter,
>
>> But Altera cannot stand to be left behind. They get creative and apply
>> a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576
>> "equivalent LUTs", thus even bigger than the Xilinx behemoth.
>
> I believe that there is a fair bit of literature explaining where the 
> multiplier comes from.  Perhaps you (and others) do not believe the 
> Stratix II vs. Virtex-4 comparison.  However, we also have data on Stratix 
> II vs. Stratix utilizaiton showing ~25% higher utilization than you would 
> expect from straight LUT/FF counting.  I certainly hope we are capable of 
> measuring our own chips.  And previous (Altera-published) results showed 
> that Stratix I achieves a higher logic density than Virtex-2.   So the 1.3 
> multiplier is at least consistant with other results.
>
> Here is a link to a white-paper comparing Stratix II and Virtex-4 logic 
> densities.  http://www.altera.com/literature/wp/wpstxiixlnx.pdf.  And here 
> is another white paper on the ALM 
> http://www.altera.com/literature/wp/wpstxiiple.pdf.
>
> There are also two academic papers published in respected, referred FPGA 
> conferences.  Both are authored by individuals who have established 
> reputations in the FPGA industry.  The first paper describes the Stratix 
> II architecture, including a section on the ALM (Lewis et al, "The Stratix 
> II logic and routing architecture", Proceedings of the 2005 ACM/SIGDA 13th 
> international symposium on FPGAs --  
> http://www.eecg.toronto.edu/~jayar/pubs/lewis/lewisfpga05.pdf).  The 
> second is specifically on the ALM (M. Hutton et al, "Improving FPGA 
> performance and area using an adaptive logic module", International 
> Conference on Field-Programmable Logic and Applications 2004).
>
> The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs 
> (like a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, 
> and other more powerful combinations (such as 2 6-LUTs that share 4 
> inputs, etc). When you technology map a design into a specific look-up 
> table (LUT) size, you get a variety of LUT sizes -- you can't map all the 
> logic to use exactly 4-inputs (for example).  Since you have a 
> distribution of LUT sizes, the capability to pair more than just 2 4-LUTs 
> into a single ALM will result in a decrease in the number of ALMs 
> required.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
> P.S. Ours is bigger -- and we can use it better too!

Well then when are you guys going to have a low cost board
similar to the spartan3 (or 3e) starter kit ?

Hi Alex,

There are two Cyclone kits sold by partners of ours that are in the
same price range:

Future $49 Cyclone/Nios II eval kit:
http://www.altera.com/products/devkits/partners/kit-future-badge.html
Altium $99 kit:
http://www.altera.com/products/devkits/partners/kit-alt-live-design.html

With Cyclone II now available, I can assure you there will be low-cost
Cyclone II dev kits available in the near future.  Sorry, but I can't
comment on exact dates.

Regards,

Paul Leventis
Altera Corp.

BTW, there are dev kits available for Cyclone II.  The DSP dev kit,
Cyclone II edition and the Nios II dev kit, Cyclone II edition (which
use an EP2C35) are now shipping. The PCI dev kit, Cyclone II edition
will start shipping next month. Customers can place orders for all
these today.

DSP: http://www.altera.com/products/devkits/altera/kit-dsp-2C35.html
Nios II:
http://www.altera.com/products/devkits/altera/kit-nios-2c35.html
PCI: http://www.altera.com/products/devkits/altera/kit-pci-2c35.html

Regards,

Paul Leventis
Altera Corp.

"Paul Leventis" <paul.leventis@utoronto.ca> schrieb im Newsbeitrag
news:1116355134.958776.172170@z14g2000cwz.googlegroups.com...
> BTW, there are dev kits available for Cyclone II.  The DSP dev kit,
> Cyclone II edition and the Nios II dev kit, Cyclone II edition (which
> use an EP2C35) are now shipping. The PCI dev kit, Cyclone II edition
> will start shipping next month. Customers can place orders for all
> these today.
>
> DSP: http://www.altera.com/products/devkits/altera/kit-dsp-2C35.html
> Nios II:
> http://www.altera.com/products/devkits/altera/kit-nios-2c35.html
> PCI: http://www.altera.com/products/devkits/altera/kit-pci-2c35.html
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>

those all are WAY over priced compared to hpe-mini
http://www.trs-asic.com

Antti
PS Paul, I recently sent you an private email, just out of curiosity did you
receive it?

"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message 
news:PaudnRAmKPtWBhTfRVn-vA@rogers.com...
> Hi Peter,
>
-snip-
> The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs 
> (like a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, 
> and other more powerful combinations (such as 2 6-LUTs that share 4 
> inputs, etc). When you technology map a design into a specific look-up 
> table (LUT) size, you get a variety of LUT sizes -- you can't map all the 
> logic to use exactly 4-inputs (for example).  Since you have a 
> distribution of LUT sizes, the capability to pair more than just 2 4-LUTs 
> into a single ALM will result in a decrease in the number of ALMs 
> required.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
> P.S. Ours is bigger -- and we can use it better too!
As a frequent Xilinx user (4K, Virtex-2, V2P, soon V4), I note that in the 
slice (2 4-input LUTs), there is also available a 3-input LUT following 
those two.  That LUT can be fed the input of [at least] one independent 
input (besides the outputs from the two 4-input LUTs), creating the 
opportunity to broaden the input set with minimal cost (delay, routing.)  I 
have also extensively used the distributed RAM (sometimes as ROM), and 
occasionally the SLR function.

I also have had occasion to use Altera, although not lately.  In '96 I had a 
design where Altera had the appropriate solution (love those embedded block 
RAMs, which Xilinx now has--features may vary), but in '97 I had a design 
where Xilinx was better from a planning perspective (read:  growth path.)

Over the past 10+ years, I've had to get "under the hood" of the Xilinx 
tools:  hand floorplanning, extensive timing constraints, reading lots of 
app notes.  So you could say that I'm fairly comfortable with their 
architecture(s) and tools.  However, I'd have to agree with some previous 
posters:  if you think you have a challenging design, evaluate what you can 
before committing.  That's what I have done in the past, and prefer to do in 
the future (though usually, I'm stuck with a pre-determined selection.) 
Typically, you can budget key resources (be that memory, LUTs, registers, 
multipliers, pins, ...)   You can also do a test-case design that tests the 
anticipated critical path.  The same principle applies for synthesis and 
simulation tools, too.

Jason 

Hi Edwin,

I'm glad you had a positive experience with Quartus and Stratix II.

I'm sorry to hear you got an unroute in one of your compiles though.  I'd 
greatly appreciate it if you could send me the design, so my team can take a 
crack at routing it.  We don't have very many unroutes these days, even at 
very high logic utilization, so case studies like this are very useful for 
improving our tools. We would use the design only to tune our tools, will 
never release it outside Altera, and frankly we won't understand your design 
as anything but a place and route problem instance anyway :).

It's most likely we can route it in house with more "routability tuned" 
compiler settings, which we will send back to you as well.

Regards,

Vaughn Betz
[v b e t z (at) altera.com]



<ecpark@gmail.com> wrote in message 
news:1116307583.701370.101440@g14g2000cwa.googlegroups.com...
> Past:  I did a lot of leading edge (in terms of size) FPGA designs for
> ASIC prototyping.   Size, usability, and cycle-time is of the essense.
> In the past, I have used Orca (1996), Virtex , VirtexE,  and V2.  About
> 5 years ago, I looked at Altera and Quartus pretty much shot them in
> the foot.
>
> Current: In the new design, I once again evaluated state of the art
> FPGAs.  For this cycle Virtex4's timeline was a little too late (by a
> couple of months), so I started in StratixII (2S130s and 2S180s).  So
> far, I have been very impressed with the tools and results.
>
> Note: Altera's FPGA is not totally symmetric.  Different types of
> memory, different type of PLLs, only certain PLLs can do feedback,
> vertical I/Os are different than horizontal I/Os.  I thought this would
> be difficult to keep straight.  However, I am getting to realize the
> design I am working on is very not symmetric, so this has not been a
> problem.
>
> Memory:  I first thought that having to worry about the different types
> of memory (512, 4K, 512K) was going to cause a accounting nightmare,
> but you can actually set it to decide for you.   Quartus decides for
> itself which one to use.  I really like this.
>
> Synthesis: I have been impressed with the synthesis results.  Not as
> good as Synplify Pro, but it comes with Quartus II.  We are having a
> problem where Synplify is not finishing on one of the FPGAs and having
> the Quartus synthesis engine saved us.  Also, synthesis in Quartus
> takes about 2x-3x more computer time than synthesis in Synplify.
>
> Physical Synthesis:  I was incredibly impressed with this since it is a
> check box (vs. psuedo-floorplanning with Amplify or hand modification
> with Precision).  For me, it is the difference between closing and not
> closing timing.  One note though, some of my design grow by 20% when I
> turn this on, so make sure you have a lot of head room.
>
> Logic: I really like the ALM.  It does cut down on the number of levels
> the logic has to go through.  This helps with timing.  Despite what
> either Altera or Xilinx have to say, I really don't need a 1:1 ratio of
> logic elements to FF.  About 10:1 ratio for ASIC prototyping is a
> better ratio.  I would really like to see what other designers see.  I
> would really like to see future families have at least 2x more logic
> vs. FFs.
>
> PLLs:  I like the analog PLLs vs. DPLLs of Xilinx.  One warning, if you
> set QuartusII to decide the PLL type, you may not get to use all the
> ratios.  Kind of bizarre, but that is the way I interpreted the tool.
> I just set to only use Enhanced and the problem went away.
>
> General: The tool flow is a little bit cleaner, but the Xilinx tool
> flow was pretty good, so that is a wash.  I am not a tcl expert, so it
> takes a little getting used to.  I do like when you finally get all the
> tcl scripts right, you don't have to remember any switches, but once
> again a wash.
>
> Support: I am getting great support both locally and from the factory.
> Of course your mileage will vary and may ultimately determine your
> choice and your success.
>
> Not used: I did not use processors, high speed transceivers, other IOs.
>
>
> Cons 1: I was playing around with some different partition and I had a
> design that was 85% full (in terms of logic) and Quartus II could no
> route it at all (with no timing constraints).  To be fair, I have other
> partitions with more than 90% that did route.  In previous Xilinx
> devices in the Virtex* family, I only had problems closing time (i.e.
> routing did not fail) at 95%, so budget your size appropriately.
>
> Cons 2: Currently, there is no flash part that could program more than
> 1 of these large devices.  It really makes the JTAG chain on the board
> needlessly complicated.
>
> -Edwin
> 

"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message 
news:1116355048.275044.78030@o13g2000cwo.googlegroups.com...
> Hi Alex,
>
> There are two Cyclone kits sold by partners of ours that are in the
> same price range:
>
> Future $49 Cyclone/Nios II eval kit:
> http://www.altera.com/products/devkits/partners/kit-future-badge.html
> Altium $99 kit:
> http://www.altera.com/products/devkits/partners/kit-alt-live-design.html
>
> With Cyclone II now available, I can assure you there will be low-cost
> Cyclone II dev kits available in the near future.  Sorry, but I can't
> comment on exact dates.
>

I have an Altium Altera board(and a xilinx one)
It doesn't come with any project file ready to use with Quartus
and you have to work out the connections as well.
Only annoyance is lack of config prom.

The lack of Quartus  project files means it is unsuitable for beginners 
unless
they are using it with the Altium software.

That future board is not even in the same league as the Spartan 3 starter 
kit.



Alex