VHDL vs. Schematic Capture

Hi Y'all :

I have many years of experience with hardware design, software design & 
implementation etc (i.e. I'm comfortable with C++, soldering or anything in 
between)

I'm using FPGA"s more and more.

So far, I've used schematic capture exclusively. I use Altera's Megawizard, 
so I know someone wrote some parameterizable VHDL behind this, but I still 
think in hardware terms.

I never learned VHDL, and wonder if it's worth it.

My take has been that I am designing hardware - configuring the LE's and 
interconnects and not writing algorithms. This seems to me to be mind-set 
that best fits what I'm doing.

I notice that a lot of people here refer to "code" - suggesting they have an 
algorithmic mind-set

What am I missing ? What would be some examples of something better done in 
VHDL ? Are there examples of stuff that cannot be done in schematic ?

Any comments will be appreciated.

Gary 

Hi

> My take has been that I am designing hardware - configuring the LE's and 
> interconnects and not writing algorithms. This seems to me to be mind-set 
> that best fits what I'm doing.
> 
> I notice that a lot of people here refer to "code" - suggesting they have an 
> algorithmic mind-set
> 
> What am I missing ? What would be some examples of something better done in 
> VHDL ? Are there examples of stuff that cannot be done in schematic ?

Well, when doing VHDL, you'd better be thinking hardware as well. VHDL 
is a language to describe the hardware you want built.

When you code in VHDL, you don't think "algorithm", you think register,
combinatorial logic and you describe that in VHDL.

Note the exception about that is when you code testbench and "code 
generation". The first is just a behovioral description of the test 
environment and stimulus and don't need to be synthetizable. The latter 
is when you write "generic" VHDL code that needs to adapt somewhat to 
static option at synthesis time (not unlike the C preprocessor).

The main advantage I see about HDL over schematic capture would be :
  - Vendor independent : I don't think the schematics are interoperable 
but I may be mistaken
  - Text edition : To write the vhdl, you can do it every where where 
you have a text editor, no need to have the vendor tools
  - Genericity : When you have a complex block that needs different fine 
tuning for different application, you can use parameters to change details.

But that's just IMHO ...

	Sylvain

"Gary Pace" <xxx@yyy.com> wrote in message 
news:5Kvje.113165$AE6.112367@tornado.texas.rr.com...
> I never learned VHDL, and wonder if it's worth it.
>
> My take has been that I am designing hardware - configuring the LE's and 
> interconnects and not writing algorithms. This seems to me to be mind-set 
> that best fits what I'm doing.
>
> I notice that a lot of people here refer to "code" - suggesting they have 
> an algorithmic mind-set
>
> What am I missing ? What would be some examples of something better done 
> in VHDL ? Are there examples of stuff that cannot be done in schematic ?

I too used schematic entry exclusively until the company ran into a larger 
project, and we got sent off on VHDL course. Now it's exclusively VHDL, not 
because there's any functional difference in my mind, but because I'm lazy.
True, I too refer to the file as 'code', but it's only 'code' or 
'behavioural description' until it's been through the synthesis tool, just 
as 'schematic' is only a 'drawing of funny looking boxes' until the 
synthesis tool breaks it down. Algorithmic mindset, no. For me that somehow 
implies sequential execution, and hardware isn't. I'm a C programmer too, 
and I tried reading VHDL from a sequential-execution mindset. It didn't 
work.

As an example (because I've done this both in schematic and VHDL), consider 
a shift/count register typically used for a reciprocal frequency counter. In 
schematic I constructed a symbol with a FF that would either count or shift, 
and made a schematic with 28 of those symbols. Draw wires, think it over, 
did I do it right, okay. If I want to expand the register, I need to draw 
more.
When writing VHDL my mindset is still "I need a register, when not gated 
open it should be a shift register, when gated open it should be a 
synchronous counter. It should be clocked from refclock."

  if rising_edge(refclk) then
    if (gate='1') then
      fcount<=fcount+1;
    else
      if (shiftpip='1') then
        fcount<=fcount(fcount'LEFT-1 downto 0) & '0';
      end if
    end if;
  end if;

Reading it goes like "There are some refclk-risingedge-clocked flipflops, 
and there's a gate-controlled multiplexer in front of them. One input has 
the output of an adder, the other the left shifted signals, and clock enable 
is gate or shiftpip." And it's faster for me to read and convince myself 
that it's right.

In my experience, once a schematic reaches the point where you think that 
you 'really have a lot of wires on this page, and which ones end up where?' 
VHDL entry handles the complexity better.

/Kasper

Gary Pace wrote:

> Hi Y'all :
> 
> I have many years of experience with hardware design, software design & 
> implementation etc (i.e. I'm comfortable with C++, soldering or anything in 
> between)
> 
> I'm using FPGA"s more and more.
> 
> So far, I've used schematic capture exclusively. I use Altera's Megawizard, 
> so I know someone wrote some parameterizable VHDL behind this, but I still 
> think in hardware terms.
> 
> I never learned VHDL, and wonder if it's worth it.
> 
> My take has been that I am designing hardware - configuring the LE's and 
> interconnects and not writing algorithms. This seems to me to be mind-set 
> that best fits what I'm doing.
> 
> I notice that a lot of people here refer to "code" - suggesting they have an 
> algorithmic mind-set
> 
> What am I missing ? What would be some examples of something better done in 
> VHDL ? Are there examples of stuff that cannot be done in schematic ?
> 
> Any comments will be appreciated.
> 
> Gary 
> 
> 

As many writers have commented you need to know hardware before you code 
VHDL -- as certain syntax & grammar of VHDL will infer logic ... Your 
extensive background in gate-level design will serve you well in VHDL.

Everything that you do in schematics you can do in VHDL i.e. as complete set
of instantiated components wired as you want. But that is a terrible waste.
Where you really win is something like a state machine where you can
describe fairly complex behaviour in a relatively small number of lines. I
have designed state machines up to 32 thousand states. Yes I did say 32
thousand and that took me about 2 weeks to enter and debug - mostly typing.
Try doing that in schematic and not making a mistake or even fixing
mistakes.

There are lots of other examples where description is quicker and more
reliable than schematic. You are also not ruled from using schematics to
view the design, or even to do critical bits in schematic, or even doing
vhdl netlist form. If you are comfortable with C++ then you will find a lot
similarities in VHDL. VHDL can be written as very abstract code or very
simple staying with a small number of constructs like if/elsif, case etc.
Personally I prefer the simple approach to VHDL but each to their own as the
saying goes.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"Gary Pace" <xxx@yyy.com> wrote in message
news:5Kvje.113165$AE6.112367@tornado.texas.rr.com...
> Hi Y'all :
>
> I have many years of experience with hardware design, software design &
> implementation etc (i.e. I'm comfortable with C++, soldering or anything
in
> between)
>
> I'm using FPGA"s more and more.
>
> So far, I've used schematic capture exclusively. I use Altera's
Megawizard,
> so I know someone wrote some parameterizable VHDL behind this, but I still
> think in hardware terms.
>
> I never learned VHDL, and wonder if it's worth it.
>
> My take has been that I am designing hardware - configuring the LE's and
> interconnects and not writing algorithms. This seems to me to be mind-set
> that best fits what I'm doing.
>
> I notice that a lot of people here refer to "code" - suggesting they have
an
> algorithmic mind-set
>
> What am I missing ? What would be some examples of something better done
in
> VHDL ? Are there examples of stuff that cannot be done in schematic ?
>
> Any comments will be appreciated.
>
> Gary
>
>

Gary Pace wrote:
> Hi Y'all :
> 
> I have many years of experience with hardware design, software design & 
> implementation etc (i.e. I'm comfortable with C++, soldering or anything in 
> between)
> 
> I'm using FPGA"s more and more.
> 
> So far, I've used schematic capture exclusively. I use Altera's Megawizard, 
> so I know someone wrote some parameterizable VHDL behind this, but I still 
> think in hardware terms.
> 
> I never learned VHDL, and wonder if it's worth it.
> 
> My take has been that I am designing hardware - configuring the LE's and 
> interconnects and not writing algorithms. This seems to me to be mind-set 
> that best fits what I'm doing.
> 
> I notice that a lot of people here refer to "code" - suggesting they have an 
> algorithmic mind-set
> 
> What am I missing ? What would be some examples of something better done in 
> VHDL ? Are there examples of stuff that cannot be done in schematic ?
> 
> Any comments will be appreciated.
> 
> Gary 
> 
> 

IMHO:

Schematic entry has always been a transitional addition to Programmable 
Logic tools, representing a merging of the old and the new. Comparing 
Schematic entry to VHDL is like comparing Hotmetal, Frontpage or some 
other WYSIWYG website design utility to HTML/XML etc. It is a tool, enjoy.

If you are considering learning VHDL (or Verilog), my advice is a 
resounding YES; Do it, learn it.

FPGA's will soon exceed present physical production limitations and we 
will have budget giga, tera and even peta gate FPGAs. VHDL makes 
designing complex and/or large hardware very easy compared to schematic 
entry; however visual descriptions are always easier on the eye.

Now the contentions stuff:

IMHO, IMHO, IMHO: (flame on!)

It is all code. VHDL and Verilog are Hardware Description Languages. 
Various 3rd Generation Languages (3GLs) like Pascal, C, Basic etc are 
Functional description languages. ALL LANGUAGES are behavioral in 
concept; they are supposed to define and/or describe a "system's" behavior.

In development circles the words "code" and "coding" are abbreviations 
borrowed from the words "encode" and "encoding". They describe the 
process (coding) and results (code) of translating a behavioral design 
from the mental landscape into a textual format; At these levels "it is 
all code".

Now let us be really outspoken:

Synthesis is not Compilation, although compilation is a form of 
synthesis. When comparing the two, people generally consider the 
outputs: compilation results in further code, now translated into binary 
form. However, compilation is more like synthesis than translation.

Does not the binary result of synthesis define how an FPGA/CPLD/PLD 
should react to stimuli. Doesn't a compiled program do the same for a 
microprocessor? GIGO, Input, Process, Output. Who cares!! The argument 
is a philosophical one and thus one of opinion anyway.

Here is a passing thought:
If ADA never existed, what format would VHDL have. VHDL's designers WERE 
influenced. If C never existed, what form would Verilog or SystemC have. 
Their designers are influenced. If chicken never existed, what would 
everything else taste like!?!

Nme. God Bless.

P.S.

IMHO: We will always have Schematic entry, humans like pictures, CAD, 
CAM, UML, SSADM, websites; we love diagrams and images, easier to digest.

Hi Gary,
    Quartus II 4.1 and newer versions have a graphical tool called the RTL 
viewer. This tool will be great for you if you want to see how the 
VHDL/Verilog/Schematic  you write translates into logic. Our customers and 
our own developers and support folks use it extensively to debug their 
circuits if they run into a problem, or to understand how logic gets 
implemented. There is also a state machine viewer built into the RTL viewer 
which will  show you the bubble diagram for your state machines written in 
HDL.

The RTL viewer can be used to see the output after the synthesis step is 
complete, but prior to Technology mapping into LUT's. There is another tool 
called the Technology Map viewer which shows you the result after Technology 
Mapping. Both Tools are available under the Tools menu and you can bring 
them up after compiling your design. As you are already using Quartus they 
are already on your desktop and one button click away.

Hope this helps,
Subroto Datta
Altera Corp.


"dave" <dave@dave.dave> wrote in message 
news:d6n75m$c0c$1@news7.svr.pol.co.uk...
> Gary Pace wrote:
>> Hi Y'all :
>>
>> I have many years of experience with hardware design, software design & 
>> implementation etc (i.e. I'm comfortable with C++, soldering or anything 
>> in between)
>>
>> I'm using FPGA"s more and more.
>>
>> So far, I've used schematic capture exclusively. I use Altera's 
>> Megawizard, so I know someone wrote some parameterizable VHDL behind 
>> this, but I still think in hardware terms.
>>
>> I never learned VHDL, and wonder if it's worth it.
>>
>> My take has been that I am designing hardware - configuring the LE's and 
>> interconnects and not writing algorithms. This seems to me to be mind-set 
>> that best fits what I'm doing.
>>
>> I notice that a lot of people here refer to "code" - suggesting they have 
>> an algorithmic mind-set
>>
>> What am I missing ? What would be some examples of something better done 
>> in VHDL ? Are there examples of stuff that cannot be done in schematic ?
>>
>> Any comments will be appreciated.
>>
>> Gary
>
> IMHO:
>
> Schematic entry has always been a transitional addition to Programmable 
> Logic tools, representing a merging of the old and the new. Comparing 
> Schematic entry to VHDL is like comparing Hotmetal, Frontpage or some 
> other WYSIWYG website design utility to HTML/XML etc. It is a tool, enjoy.
>
> If you are considering learning VHDL (or Verilog), my advice is a 
> resounding YES; Do it, learn it.
>
> FPGA's will soon exceed present physical production limitations and we 
> will have budget giga, tera and even peta gate FPGAs. VHDL makes designing 
> complex and/or large hardware very easy compared to schematic entry; 
> however visual descriptions are always easier on the eye.
>
> Now the contentions stuff:
>
> IMHO, IMHO, IMHO: (flame on!)
>
> It is all code. VHDL and Verilog are Hardware Description Languages. 
> Various 3rd Generation Languages (3GLs) like Pascal, C, Basic etc are 
> Functional description languages. ALL LANGUAGES are behavioral in concept; 
> they are supposed to define and/or describe a "system's" behavior.
>
> In development circles the words "code" and "coding" are abbreviations 
> borrowed from the words "encode" and "encoding". They describe the process 
> (coding) and results (code) of translating a behavioral design from the 
> mental landscape into a textual format; At these levels "it is all code".
>
> Now let us be really outspoken:
>
> Synthesis is not Compilation, although compilation is a form of synthesis. 
> When comparing the two, people generally consider the outputs: compilation 
> results in further code, now translated into binary form. However, 
> compilation is more like synthesis than translation.
>
> Does not the binary result of synthesis define how an FPGA/CPLD/PLD should 
> react to stimuli. Doesn't a compiled program do the same for a 
> microprocessor? GIGO, Input, Process, Output. Who cares!! The argument is 
> a philosophical one and thus one of opinion anyway.
>
> Here is a passing thought:
> If ADA never existed, what format would VHDL have. VHDL's designers WERE 
> influenced. If C never existed, what form would Verilog or SystemC have. 
> Their designers are influenced. If chicken never existed, what would 
> everything else taste like!?!
>
> Nme. God Bless.
>
> P.S.
>
> IMHO: We will always have Schematic entry, humans like pictures, CAD, CAM, 
> UML, SSADM, websites; we love diagrams and images, easier to digest. 

Subroto Datta wrote:
> Hi Gary,
>     Quartus II 4.1 and newer versions have a graphical tool called the RTL 
> viewer. This tool will be great for you if you want to see how the 
> VHDL/Verilog/Schematic  you write translates into logic. Our customers and 
> our own developers and support folks use it extensively to debug their 
> circuits if they run into a problem, or to understand how logic gets 
> implemented. There is also a state machine viewer built into the RTL viewer 
> which will  show you the bubble diagram for your state machines written in 
> HDL.
> 
> The RTL viewer can be used to see the output after the synthesis step is 
> complete, but prior to Technology mapping into LUT's. There is another tool 
> called the Technology Map viewer which shows you the result after Technology 
> Mapping. Both Tools are available under the Tools menu and you can bring 
> them up after compiling your design. As you are already using Quartus they 
> are already on your desktop and one button click away.
> 
> Hope this helps,
> Subroto Datta
> Altera Corp.
> 

You guys working weekends as well now?

Will Quartus be available in a Linux release soon or has this occured 
already. If yes, where, when and how much.......

Nme. God Bless.

Hi Dave,

    Quartus has been available on Linux for the past two years. Red Hat 
Version 7.3, 8.0 and Red Hat Enterprise 3.0 are supported with Quartus II 
5.0. We will be dropping 7.3 in the next release. These have been tested 
with both Opteron and Xeon CPU's. Based on comments from some of the power 
Linux users they have had it working on other Linux distributions. This 
product will require the purchase of a Linux subscription. You will need to 
contact your distributor or the Altera Telsesales group depending on your 
location. Check http://www.shopaltera.com/design_software.asp for contact 
information.

Hope this helps,
- Subroto Datta
Altera Corp.


"dave" <dave@dave.dave> wrote in message 
news:d6ndja$jpi$1@news6.svr.pol.co.uk...

> You guys working weekends as well now?
>
> Will Quartus be available in a Linux release soon or has this occured 
> already. If yes, where, when and how much.......
>
> Nme. God Bless. 

Gary Pace wrote:

>Hi Y'all :
>
>I have many years of experience with hardware design, software design & 
>implementation etc (i.e. I'm comfortable with C++, soldering or anything in 
>between)
>
>What am I missing ? What would be some examples of something better done in 
>VHDL ? Are there examples of stuff that cannot be done in schematic ?
>  
>
I also like schematics for "random" logic, such as a bus controller/decoder.

But, there's some stuff that is just so much more concise in VHDL.  One 
example
is a Gray-binary or binary-Gray code converter.  In schematic, it is a 
string
of FFs and XORs.  In VHDL, it is a parameterizable one-line statement, with
the parameter being the # of bits.  (I may be exaggerating the 
concise-ness just
a little, but both of these functions were completely coded in 4-6 lines.)
These were 48-bit converters for time codes.

I also did an experiment just to stretch my VHDL writing skills and coded up
a do-nothing box that (pseudo)randomly changed bits in a 10 x 10 array, 
and simultaneously
refreshed a 10 x 10 grid of LEDs, like a raster scan.  Each of those 
bits was a
VHDL function, and each raster line looped through 10 bits, then the 
line looped
through 10 iterations.  I compared (mentally) what this would look like 
in the most
concise hierarchical schematic, and the superiority of the HDL was 
pretty convincing.

Jon