How to make a 1.44MHz clock?

Hello,
I have a spartan 3 starter board with 50MHz oscillator.

I need to generate a 1.44MHz clock to drive an external port and some
internal logic block such as counters, comparators, etc.

I have tried with a series of 2 DCM, but I have obtained a very different
period.

What I could do?


Thanks
Marco Toschi

If you can tolerate some jitter in your clock you can use a NCO for the
generation of your required frequency. If you are not familiar with
this term (NCO) search for it in this forum.
I hope it helps..
Moti Cohen.

Marco wrote:
> Hello,
> I have a spartan 3 starter board with 50MHz oscillator.
> 
> I need to generate a 1.44MHz clock to drive an external port and some
> internal logic block such as counters, comparators, etc.
> 
> I have tried with a series of 2 DCM, but I have obtained a very different
> period.
> 
> What I could do?
> 
> 
> Thanks
> Marco Toschi

Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in 
frequency synthesis mode to get an 18/25 multiplier (36 MHz).  Use that 
for your internal clock WITH a clock-enable for the whole thing once 
every 25 cycles.  Also use that clock enable to drive an IOB register 
high which you then deassert 12 or 13 36 MHz clocks later for 48%/52% 
duty cycle.

Clean, workable.

"John_H" <johnhandwork@mail.com> wrote in message
news:FuIje.3028$6d.1773@trnddc02...
> Marco wrote:
> > Hello,
> > I have a spartan 3 starter board with 50MHz oscillator.
> >
> > I need to generate a 1.44MHz clock to drive an external port and some
> > internal logic block such as counters, comparators, etc.
> >
> > I have tried with a series of 2 DCM, but I have obtained a very
different
> > period.
> >
> > What I could do?
> >
> >
> > Thanks
> > Marco Toschi
>
> Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> frequency synthesis mode to get an 18/25 multiplier (36 MHz).  Use that
> for your internal clock WITH a clock-enable for the whole thing once
> every 25 cycles.  Also use that clock enable to drive an IOB register
> high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> duty cycle.
>
> Clean, workable.


To enable clock every 25 cycles I have used a counter with a threshold
signal that goes high at cycle 25.
The threshold signal will be the Clock enable for other logic blocks.

But in this way I obtain a gated clock on this counter.

What could I do?

I thought to the following circuit:
          ___________________________________
          |
|
          --------|          |                                             |
                      | MUX |-------------|D    FF    Q|------------- Clock
Enable
Counter ------|          |                    |                  |
                            |                                   |
                            |                                   |
                            ------------------------
                                             |
                                         oscillator

Is it correct?

Thanks
Marco Toschi

"John_H" <johnhandwork@mail.com> wrote in message
news:FuIje.3028$6d.1773@trnddc02...
> Marco wrote:
> > Hello,
> > I have a spartan 3 starter board with 50MHz oscillator.
> >
> > I need to generate a 1.44MHz clock to drive an external port and some
> > internal logic block such as counters, comparators, etc.
> >
> > I have tried with a series of 2 DCM, but I have obtained a very
different
> > period.
> >
> > What I could do?
> >
> >
> > Thanks
> > Marco Toschi
>
> Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> frequency synthesis mode to get an 18/25 multiplier (36 MHz).  Use that
> for your internal clock WITH a clock-enable for the whole thing once
> every 25 cycles.  Also use that clock enable to drive an IOB register
> high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> duty cycle.
>
> Clean, workable.

Bad design...

I hope this is better...

          ________________________________
          |                                                                |
          --------|          |                                         |
                      | MUX |--------|D    FF    Q|--------Clock_En
Counter ------|          |             |                  |
                            |                              |
                            |                              |
                            ---------------------
                                             |
                                         oscillator

Marco, all you have to do is build a 5-bit synchronous counter, clocked
at 36 MHz, that divides by 25, and decode one period of the 25. Pick
the period that is easiest to decode.
Use that decoded signal (active High) as the CE input to all your 1.44
MHz flip-flops.
Xilinx does the rest for you. CE controls a mux in front of the D input
that makes the D equal to Q whenever the flip-flop should not change
("clock disable").
This mux is invisible to you, and it means that the clock never is
gated.
Easy!
Peter Alfke, Xilinx Applictions

Peter Alfke wrote:

> Marco, all you have to do is build a 5-bit synchronous counter,
clocked
> at 36 MHz, that divides by 25, and decode one period of the 25. Pick
> the period that is easiest to decode. Use that decoded signal (active
High)
> as the CE input to all your 1.44 MHz flip-flops.

He also needs to drive an external 1.44 MHz clock signal...

Arlet

As John_H explained, he can derive the 1.44 MHz clock from the
divide-by-25 counter, either synchronously or by decoding. But he may
have to pay attention to the phase relationship between the internal
1.44 MHz operation (which is synchronous to the 36-MHz clock, and the
1.44 MHz clock being sent out.
Considering the low freqiencies involved, there is enormous leeway...
Peter Alfke

An example in Verilog:

always @(posedge Clk_36MHz)
begin  // counting 0-24, inclusive
  count <= count + (enable ? -5'd24 : +5'd1);
  enable <= (count==5'd24);
  out_clk <= enable | (count<5'd12);
  if( enable )
  begin
    // do everything here at
    // 1.44 MHz, no gated clock
  end
end

A gated clock would be:

wire ClkGated = Clk36MHz | ~enable;
always @(posedge ClkGated)
begin
  // do everything at 1.44 MHz with severe clock skew
end

Which - it appears you know - isn't a great way to go.


"Marco" <marcotoschi_no_spam@email.it> wrote in message
news:d6plfi$o79$1@news.ngi.it...
<snip>
> > > What I could do?

<snip>

> > Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> > frequency synthesis mode to get an 18/25 multiplier (36 MHz).  Use that
> > for your internal clock WITH a clock-enable for the whole thing once
> > every 25 cycles.  Also use that clock enable to drive an IOB register
> > high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> > duty cycle.
> >
> > Clean, workable.

<snip>

My Outlook Express or appears to have the code snippet excerpted as a
(non-readable) attachment.
Trying again:

An example in Verilog:

  always @(posedge Clk_36MHz)
  begin  // counting 0-24, inclusive
    count <= count + (enable ? -5'd24 : +5'd1);
    enable <= (count==5'd24);
    out_clk <= enable | (count<5'd12);
    if( enable )
    begin
      // do everything here at
      // 1.44 MHz, no gated clock
    end
  end

A gated clock would be:

  wire ClkGated = Clk36MHz | ~enable;
  always @(posedge ClkGated)
  begin
    // do everything at 1.44 MHz with severe clock skew
  end

Which - it appears you know - isn't a great way to go.



> "Marco" <marcotoschi_no_spam@email.it> wrote in message
> news:d6plfi$o79$1@news.ngi.it...
> <snip>
> > > > What I could do?
>
> <snip>
>
> > > Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM
in
> > > frequency synthesis mode to get an 18/25 multiplier (36 MHz).  Use
that
> > > for your internal clock WITH a clock-enable for the whole thing once
> > > every 25 cycles.  Also use that clock enable to drive an IOB register
> > > high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> > > duty cycle.
> > >
> > > Clean, workable.
>
> <snip>
>
>