Interesting article about FPGAs

A good read for anyoane interested in FPGA
http://www.embedded.com/showArticle.jhtml?articleID=15201141
---
jakab

That was a good read.  Of course, anything that says FPGA designers will
have a bright and glorious future is always nice ;_)

Thanks jakab

From the article:
  Antifuse also has some power consumption advantages over SRAM.

Can anybody explain that to me?  Perhaps that refers to static current?

[The SRAM part of an SRAM FPGA doesn't change during normal operation
so the F part of C*V^2*F is 0.]


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Hal,

Here's my best guess for why an anti-fuse FPGA could have lower dynamic
power (I don't know if this is the case):  If I recall correctly, anti-fuse
FPGAs can do some forms of switching with direct metal-to-metal connection
through anti-fuse vias.  In an SRAM FPGA, all switching must be done through
SRAM-controlled multiplexors & buffers.  The additional switches in a given
route increase the C and (maybe) add more crow-bar current during switching.
Also, many of the transistors in the muxing fabric are off during operation.
So you've got more transistors (higher static power) and more dynamic power.

- Paul

There's one thing Zeidman mentions that I feel very strongly about.  In
fact, I've been repeating a phrase very similar to the one he used in the
article for about four years now:  WE NEED BETTER TOOLS.

I sincerely think that FPGA manufacturers need to figure out a way to get
out of the tool business and pour their resources into making better chips.
Open it up to the masses.  The first company to do that is bound to take a
big huge bite out of the other's market share simply because of all the
tools that will be offered by the engineering community.  There's probably a
ton of very capably and creative guys out there who are ready, eager and
able to create wonderful new --and very powerful-- tools with which to craft
designs.  Instead, we are gang-chained to the vision and approach offered by
the vendors.

Well meaning as they might be, I doubt that any real progress will come out
of their shops.  Just incremental improvements, but that's it.  For example:
Why is it that I can't use a farm of twenty PC's to compile a complex design
quckly?

When your very survival as a business is predicated upon how well your
product performs in a free market, the best tools tend to float to the top
and others fizzle.  No FPGA manufacturer's survival, at the current stage of
things, depends on the quality of their tools.  As long as they are adequate
engineers make them work.  What us end-users want are the chips, so we
put-up with whatever we are forced to use in order to put the chips on our
boards.  If a better tool appeared we'd probably drop the current offerings
in a nanosecond.


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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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"jakab tanko" <jtanko@ics-ltd.com> wrote in message
news:bljsjs$4me$1@news.storm.ca...
> A good read for anyoane interested in FPGA
> http://www.embedded.com/showArticle.jhtml?articleID=15201141
> ---
> jakab
>
>

Martin Euredjian wrote:
> 
> There's one thing Zeidman mentions that I feel very strongly about.  In
> fact, I've been repeating a phrase very similar to the one he used in the
> article for about four years now:  WE NEED BETTER TOOLS.
> 
> I sincerely think that FPGA manufacturers need to figure out a way to get
> out of the tool business and pour their resources into making better chips.
> Open it up to the masses.  The first company to do that is bound to take a
> big huge bite out of the other's market share simply because of all the
> tools that will be offered by the engineering community.  There's probably a
> ton of very capably and creative guys out there who are ready, eager and
> able to create wonderful new --and very powerful-- tools with which to craft
> designs.  Instead, we are gang-chained to the vision and approach offered by
> the vendors.
> 
> Well meaning as they might be, I doubt that any real progress will come out
> of their shops.  Just incremental improvements, but that's it.  For example:
> Why is it that I can't use a farm of twenty PC's to compile a complex design
> quckly?
> 
> When your very survival as a business is predicated upon how well your
> product performs in a free market, the best tools tend to float to the top
> and others fizzle.  No FPGA manufacturer's survival, at the current stage of
> things, depends on the quality of their tools.  As long as they are adequate
> engineers make them work.  

and if they are in-adequate, engineers choose another vendor - so FPGA
vendors
are actually VERY dependant on tool quality.

> What us end-users want are the chips, so we
> put-up with whatever we are forced to use in order to put the chips on our
> boards.  If a better tool appeared we'd probably drop the current offerings
> in a nanosecond.

 It depends very much where in the tool chain you mean.
 For front end, silicon independant compilers/simulators, then there is
scope for
any tool chain to create a connectivity file.
 What you need here is enough competent designers, with enough spare
time....

 For back end tools, and some IP generators, that have to map closely to 
the silicon, then it is not practical to 3rd party that. Tools would
come
out MUCH later, or the silicon would have to 'freeze' features.

 If there are features you want to see, then talk with the FPGA
vendors....

-jg

"Jim Granville" wrote:

> and if they are in-adequate, engineers choose another vendor - so FPGA
> vendors are actually VERY dependant on tool quality.

I don't think you got my point.  Tools today are adequate.  And that's it.
Without competition the rate of progress is slow.  So everyone deals with it
and life goes on.  But, you only have one choice per vendor.  So, as long as
the pain/results threshold is on the correct side of the scale, vendors are
safe and few are going to switch chips and redo complete designs just 'cause
of the tools.  In some companies managers would let an engineer pop a blood
vessel before incurring the additional cost of a redesign just 'cause the
FPGA guy is complaining.  If there was real competition things would be
different.

Take hierarchical floorplanning, for example.  Badly needed.  Nowhere in
sight.
Or more intelligent routers.
Or RPM's that contain more than just placement.
How about parallel processing (network-based, bunch of cheap computers) to
speed up compile runs that take too long?
How about better design entry environments (recent thread about editors is
one example).
Or better documentation.
Etc., etc.

Take something like Xilinx's Incremental flow.  Sounds great, but, if you
instantiate a module more than once you can't use that approach on it.  Why?
And, depending on how which documents you read, it doesn't work with
submodules in a hierarchy, only modules instantiated in the top level.  If
this is the case, why?  I have a fair degree of certainty that an
independent developer would not take this approach, cause the competition
would tear them to shreads.

An open market and real competition would no doubt result in a quantum leap
in FPGA design tool quality.  I have no doubts about this.  The problem is
that the critical bits of info are not available for anyone to even attempt
to generate their own bit files.

Compare the FPGA world to the embedded/C world.  Most microcontroller
manufacturers' compilers stink.  There are a number of great compilers and
design environments out there available from various companies.  Some are
wonderful.  Some are not.  Others are free.  And, of course, there are those
that are too expensive.  But, you have choices, and companies dedicated to
that small segment of the business have proven that they can do a better job
than the chip manufacturers.


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Martin Euredjian

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Boy, how long have you been in the business? The tools these days are
excellent. That's not to say they can't be improved, because they can.
I recall hand routing fpga designs and thinking I was in 7th heaven.
But, then, I have done designs with hand drawn schematics and
wire-wrapped TTL logic (I had a drafting board & machine until a
couple of years ago).

20+ years.  I go back to hand-drawn schematics and wire-wrapped boards as
well.  Had lots of fun designing boards the size of pizza boxes with loads
of TTL chips.

Don't be fooled by shinny GUI's.  Today's tools are adequate.  Not sure I'd
call them good.
I have a feeling they need to (and could/should) be substantially better.
And I simply don't think that sole-sourcing is the way to go.  Not any more.
That's all.

-Martin


"Tom Seim" <soar2morrow@yahoo.com> wrote in message
news:6c71b322.0310042218.5ca0dfba@posting.google.com...
> Boy, how long have you been in the business? The tools these days are
> excellent. That's not to say they can't be improved, because they can.
> I recall hand routing fpga designs and thinking I was in 7th heaven.
> But, then, I have done designs with hand drawn schematics and
> wire-wrapped TTL logic (I had a drafting board & machine until a
> couple of years ago).

[Opinions below are my own]

Martin,

I must say, as an FPGA software developer I disagree with most of what you
have to say.  Altera (and I'm sure Xilinx too) has 100's of sw engineers
banging on the software at any given time.  Software can be a great
differentiator -- in the past 10 years, there have been times when a company
has pulled ahead on the basis of better software, or fell behind due to
buggy/unstable software.  Most customers don't pick our chips until they've
tried them out, and that means using the software.  Once someone has
committed to a given vendor's chips, they won't change chips just because of
software.  But a bad software experience can certainly influence a
customer's future vendor decision!

Now, you can argue this means we've brought the software up to "adequate"
levels.  But then why would we be constantly adding new features and
improving tool quality?  We feel the competitive pressure -- even in a
two-horse race you have to gallop as fast as you can.

To address a few of the features you point out as being in need:

- Hierarchical floorplanning.  I believe that you can make hierarchical
LogicLock constraints in Quartus.  I'm not sure if that meets your needs,
but if it doesn't you're welcome to build your own floorplanning tool and
pass constraints into Quartus.  There are 3rd party companies who have done
this.

- More intelligent routers.  What is lacking in current routers?  The
Quartus router is fully timing driven, and comes mighty close to the
best-possible routes even in the presence of congestion.  It inserts routing
to resolve hold-time.  What more do you want than a router that meets your
timing requirements, fits your design even if badly congested, and
automatically resolves hold-time issues?

- Parallel processing.  It is not easy to make a fine-grained parallel
algorithm.  Let's ignore FPGA vendors for a second.  Academics have been
trying to make parallel CAD for FPGAs/ASICs work for years.  I don't think
anyone has come up with a good solution.  The problem is that in placement
(a large part of compile time), everything is related to everything else.
So you have a lot of inter-process communication in order to keep the state
of independent processes from going stale.  You can do things like periodic
updates, etc. but then the resulting placements could have much worse
performance.  What you can do with FPGA tools is farm off multiple compiles
to different machines -- you could do a "seed sweep" to find the best
placement & routing.  Not ideal, but can be helpful at times.

- Design Entry Environments.  Agreed -- and I believe there are a number of
3rd party tools for this.  The inputs to FPGA tools are well documented so
that 3rd party vendors can write their own HDL environments and/or do their
own synthesis & placement.


I do believe that with more players in the tool market there would be more
novel ideas.  The 3rd party synthesis vendors have added all sorts of
features to their tools and new tool flows that the FPGA vendors have yet to
offer.  The area where the most innovation is needed is in front-end tools &
design entry.  I would argue that back-end tools (i.e. placement, routing,
and bit file generation) wouldn't benefit much from more documentation/open
standards.  There is a huge amount of complexity associated with creating a
functional bit stream for a REAL fpga design, and your average coder at home
won't be able to contribute much to the process.

Just my $0.02 worth.  This is an interesting thread...

- Paul Leventis
Altera Corp.