more and more and more issues with Xilinx tools

Hi all,

FPGA are fun to work with ... when the tools work.
New versions of the tools come out, then serice packs, but there is no light
that the tools would actually work better. This is towards Xilinx tools. I
used lately also Quartus 4.2 for several desings and dont recall having any
tool related issues at all.

http://wiki.openchip.org/index.php/ISE

there are some my current identified problems with ISE 7.1, unfortunatly
backing up to 6.3 doesnt also work for me as the most needed feature has a
problem on 6.3 - chipscope core inserter makes the working design a non
working design.

I can not belive that everything do try todo with Xilinx tools is so weird
that nobody else (e.g. xilinx internal testing team) has ever tried that.
But with almost anything I touch I see the tools either crash or not
properly working.

Some issues are minor, and I can figure out some workarounds, that takes
time, but if the problem can be circumvented its ok. Some issues are more
fatal. At the moment the current state (of xilinx tools) really doesnt look
like the next service pack would resolve the major issues (those I am aware
of, there are mort likely many more of them).

At the very present moment I am really in not good mood as I need to verify
some designs VERY URGENTLY and the tools just fail there where I need them.

Antti

On Mon, 23 May 2005 18:29:56 +0200, "Antti Lukats" <antti@openchip.org> wrote:

>Hi all,
>
>FPGA are fun to work with ... when the tools work.
>New versions of the tools come out, then serice packs, but there is no light
>that the tools would actually work better. This is towards Xilinx tools. I
>used lately also Quartus 4.2 for several desings and dont recall having any
>tool related issues at all.
>
>http://wiki.openchip.org/index.php/ISE
>
>there are some my current identified problems with ISE 7.1, unfortunatly
>backing up to 6.3 doesnt also work for me as the most needed feature has a
>problem on 6.3 - chipscope core inserter makes the working design a non
>working design.
>
>I can not belive that everything do try todo with Xilinx tools is so weird
>that nobody else (e.g. xilinx internal testing team) has ever tried that.
>But with almost anything I touch I see the tools either crash or not
>properly working.
>
>Some issues are minor, and I can figure out some workarounds, that takes
>time, but if the problem can be circumvented its ok. Some issues are more
>fatal. At the moment the current state (of xilinx tools) really doesnt look
>like the next service pack would resolve the major issues (those I am aware
>of, there are mort likely many more of them).
>
>At the very present moment I am really in not good mood as I need to verify
>some designs VERY URGENTLY and the tools just fail there where I need them.
>
>Antti

Have you reported the issues to Xilinx ? 
I was at a seminar last week & a Xilinx guy said they are always keen to get hold of designs (under
NDA if necessary) that break their tools so they can improve them.

"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag
news:436491941l4r0s9cvt5pkp6u1526fute26@4ax.com...
> On Mon, 23 May 2005 18:29:56 +0200, "Antti Lukats" <antti@openchip.org>
wrote:
>
> >Hi all,
> >
> >FPGA are fun to work with ... when the tools work.
> >New versions of the tools come out, then serice packs, but there is no
light
> >that the tools would actually work better. This is towards Xilinx tools.
I
> >used lately also Quartus 4.2 for several desings and dont recall having
any
> >tool related issues at all.
> >Antti
>
> Have you reported the issues to Xilinx ?
> I was at a seminar last week & a Xilinx guy said they are always keen to
get hold of designs (under
> NDA if necessary) that break their tools so they can improve them.
>

have reported some, but have not opened any webcases lately, just hasnt
enought time for that.

the current major problem I have, seems only to be an issue of core inserter
in 6.3
so using core generator and hand wiring what is more time consuming, well if
it works
and doesnt brake the desing I am happy with that for the moment. As of most
other
issues those are not so urgent burning so I can wait and see if the issues
get fixed
in next service packs.

some issues are on my side too, namly I am refusing to have 3rd PC for
xilinx design
having only 2 seems to be insufficient

Antti

"Antti Lukats" <antti@openchip.org> wrote in message
news:d6t5jr$dga$04$1@news.t-online.com...
>
> have reported some, but have not opened any webcases lately, just hasnt
> enought time for that.
>
..but you do have time to post on CAF about it? ;-)

Cheers, Syms.

"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag
news:42922978$0$79459$14726298@news.sunsite.dk...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:d6t5jr$dga$04$1@news.t-online.com...
> >
> > have reported some, but have not opened any webcases lately, just hasnt
> > enought time for that.
> >
> ..but you do have time to post on CAF about it? ;-)
>
> Cheers, Syms.
>
>
sometimes, yes :)
honeslty I was about to submit a web case a few week ago, but wasnt
succesful at first attempt and later have not tried. as of the transition
time from 6 to 7 its not so clear if it makes sense to submit bugs to
version 6, after upgrading one PC to 7.1 I have not been able to recheck if
the bugs with 6.3 I did see are fixed or not. So that one reason why I
havent submittted the webcases.

Antti

Thanks!

"Matthieu MICHON" <matthieu.michonRemove@laposte.net> schrieb im Newsbeitrag
news:42927bcd$0$4866$626a14ce@news.free.fr...
> Antti Lukats wrote:
> (...)
> > the current major problem I have, seems only to be an issue of core
inserter
> > in 6.3
> (...)
> > Antti
>
> Hi Antti
>
>
> I experienced the same issue. It seems that the RPM implementation in
> ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active
> by default in the CSP Core Inserter, the design implementation is very
> likely to fail with default settings.
>
> A simple turn-around is to un-check the "Use RPMs" attribute (located in
> the Device panel of the CSP Core Interter).
>
> Hope this help   ;)
>
>
> Matthieu (who also would be pleased to see native Mac OS X support for
> EDA tools)

Thanks!

Antti,
is hopefully not attacted for saying thanks in both top and bottom posting
style :)

Antti Lukats wrote:
> Hi all,
>
> FPGA are fun to work with ... when the tools work.
> New versions of the tools come out, then serice packs, but there is
no light
...
>
> At the very present moment I am really in not good mood as I need to
verify
> some designs VERY URGENTLY and the tools just fail there where I need
them.
>
> Antti

I have some suggestions to Xilinx about the ise7.1
regarging the intaller etc. Since they are mostly not bugs, I thought
may be I will just keep them
under the page

http://www.geocities.com/eda4linux/ise/Q2xlx.txt

Mostly started with the frustrating experiance I had downloading the
tool. I had tried 48Kbps, 28Kpbs speeds and gave up because of the
restrictions the cafes have ( since I don't access
from a company - I am not working for any currently), then I went
downloading at around
7Kbps and it tooks around 18 hours to get the
file. I heard that there are times when people had to lock up their
phones for days to get the files!. I suppose there are others with same
issues too!. I hope even the device support files can be
made into seperate downloads.
Final comment is about the performance issues I had. It
starts with opening gui stuff.

Anyways please have a look at the text and please comment.

Thanks,
George

Matthieu MICHON wrote:>
> I experienced the same issue. It seems that the RPM implementation in 
> ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active 
> by default in the CSP Core Inserter, the design implementation is very 
> likely to fail with default settings.
> 
> A simple turn-around is to un-check the "Use RPMs" attribute (located in 
> the Device panel of the CSP Core Interter).
> 

Yep, I have ended up doing the same thing. It appears to me that the 
"Use RPMs" in 6.3 is broken.

Hi Antti,

I agree with everything you said.
I also encountered the ChipScope issue on a Virtex4 design with the
ISE7.1 tools. Either disabling the "Use SRL16" or disabling the "Use
RPM" provided a good workaround.
One more problem I had to find out the hard way : if you are planning
to use the new IDELAY feature in Virtex4 (e.g.for source-synchronous
interfaces, or DDR/DDR2 interfaces as generated by the Xilinx MIG tool)
you MUST have at least ISE7.1 SP2. And also if you are using IDELAY,
you should (according to the user guide) also use the IDELAYCTRL block
: but don't wait for the IDELAYCTRLRDY pin to go high (like the user
guide says you should), because there's a bug in the bitgen tools that
prohibit this.
Maybe all this does not apply to your design, but if it does, this
saves you a LOT of debugging time :-)

best regards,
Bart De Zwaef

Antti Lukats wrote:
(...)
> the current major problem I have, seems only to be an issue of core inserter
> in 6.3
(...)
> Antti

Hi Antti


I experienced the same issue. It seems that the RPM implementation in 
ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active 
by default in the CSP Core Inserter, the design implementation is very 
likely to fail with default settings.

A simple turn-around is to un-check the "Use RPMs" attribute (located in 
the Device panel of the CSP Core Interter).

Hope this help   ;)


Matthieu (who also would be pleased to see native Mac OS X support for 
EDA tools)