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Mapping problem due to invalid pins in UCF file

Started by methi ●May 23, 2005
Hi..
I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I
tried adding some extra inputs and outputs to the top level entity and
hence made the corresponding changes to the UCF file.
But when I try implementing the design, it shows errors in the Map
process as follows:
1) The extra inputs I added in the UCF file are shown as invalid

I have just used the format

for example:

NET "my_input_name"  LOC = "P34" ;

2)Should I also add INST?

If so how should I do that and is it for all the component
instantiations?

3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?

I then removed the unused inputs and outputs but it still shows the
same error...

Any suggestions are welcome..

Thanks in advance,

Methi
Reply by Aurelian Lazarut ●May 24, 20052005-05-24
Methi,
Can you post the error message from Map?
Aurash
methi wrote:


>Hi..
>I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I
>tried adding some extra inputs and outputs to the top level entity and
>hence made the corresponding changes to the UCF file.
>But when I try implementing the design, it shows errors in the Map
>process as follows:
>1) The extra inputs I added in the UCF file are shown as invalid
>
>I have just used the format
>
>for example:
>
>NET "my_input_name"  LOC = "P34" ;
>
>2)Should I also add INST?
>
>If so how should I do that and is it for all the component
>instantiations?
>
>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
>
>I then removed the unused inputs and outputs but it still shows the
>same error...
>
>Any suggestions are welcome..
>
>Thanks in advance,
>
>Methi
>
>  
>



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply by methi ●May 24, 20052005-05-24
Hi Aurash,

These are the error messages:

ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such
site on
ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such
site on
ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid: No
such site
ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
site on the
ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such
site on
ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is invalid:
No such
ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such
site on
ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site
on the
ERROR: MAP failed

Thankyou,
Methi


Aurelian Lazarut wrote:

> Methi,
> Can you post the error message from Map?
> Aurash
> methi wrote:
>
> >Hi..
> >I am currently working with Xilinx ISE 6.3i ..The design is in

VHDL..I

> >tried adding some extra inputs and outputs to the top level entity

and

> >hence made the corresponding changes to the UCF file.
> >But when I try implementing the design, it shows errors in the Map
> >process as follows:
> >1) The extra inputs I added in the UCF file are shown as invalid
> >
> >I have just used the format
> >
> >for example:
> >
> >NET "my_input_name"  LOC = "P34" ;
> >
> >2)Should I also add INST?
> >
> >If so how should I do that and is it for all the component
> >instantiations?
> >
> >3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
> >
> >I then removed the unused inputs and outputs but it still shows the
> >same error...
> >
> >Any suggestions are welcome..
> >
> >Thanks in advance,
> >
> >Methi
> >
> >
> >
>
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324
Reply by Sean Durkin ●May 24, 20052005-05-24
methi wrote:

> Hi Aurash,
> 
> These are the error messages:
> 
> ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid:
> No such site on


This basically tells you that there is no pin "P130" on your FPGA, which
is understandable... Haven't seen any FPGAs with 130 rows/columns around
lately :) You're trying to route the signal dig_video_out<3> to a pin
that does not exist. Same with most of the other signals, your FPGA
can't possibly have pins like that. Check your pin assigments again.

cu,
Sean
Reply by Aurelian Lazarut ●May 24, 20052005-05-24
what part/package are you targeting?
Aurash
methi wrote:


>Hi Aurash,
>
>These are the error messages:
>
>ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such
>site on
>ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such
>site on
>ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid: No
>such site
>ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
>site on the
>ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such
>site on
>ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is invalid:
>No such
>ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such
>site on
>ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site
>on the
>ERROR: MAP failed
>
>Thankyou,
>Methi
>
>
>Aurelian Lazarut wrote:
>  
>
>>Methi,
>>Can you post the error message from Map?
>>Aurash
>>methi wrote:
>>
>>    
>>
>>>Hi..
>>>I am currently working with Xilinx ISE 6.3i ..The design is in
>>>      
>>>
>VHDL..I
>  
>
>>>tried adding some extra inputs and outputs to the top level entity
>>>      
>>>
>and
>  
>
>>>hence made the corresponding changes to the UCF file.
>>>But when I try implementing the design, it shows errors in the Map
>>>process as follows:
>>>1) The extra inputs I added in the UCF file are shown as invalid
>>>
>>>I have just used the format
>>>
>>>for example:
>>>
>>>NET "my_input_name"  LOC = "P34" ;
>>>
>>>2)Should I also add INST?
>>>
>>>If so how should I do that and is it for all the component
>>>instantiations?
>>>
>>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
>>>
>>>I then removed the unused inputs and outputs but it still shows the
>>>same error...
>>>
>>>Any suggestions are welcome..
>>>
>>>Thanks in advance,
>>>
>>>Methi
>>>
>>>
>>>
>>>      
>>>
>>--
>> __
>>/ /\/\ Aurelian Lazarut
>>\ \  / System Verification Engineer
>>/ /  \ Xilinx Ireland
>>\_\/\/
>> 
>>phone:	353 01 4032639
>>fax:	353 01 4640324
>>    
>>
>
>  
>



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply by methi ●May 24, 20052005-05-24
Hi Aurash and Sean..

Thanks for helping me out..

I am using XC3S400_4TQ144....

There are totally 144 pins...

And the connections have been made on the board..but the FPGA isnt
programmed as yet...

Thats what I was trying to do...program it...give the same pins to the
variables in the UCF...

Thanks,
Methi..
Aurelian Lazarut wrote:

> what part/package are you targeting?
> Aurash
> methi wrote:
>
> >Hi Aurash,
> >
> >These are the error messages:
> >
> >ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No

such

> >site on
> >ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No

such

> >site on
> >ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid:

No

> >such site
> >ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
> >site on the
> >ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No

such

> >site on
> >ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is

invalid:

> >No such
> >ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No

such

> >site on
> >ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such

site

> >on the
> >ERROR: MAP failed
> >
> >Thankyou,
> >Methi
> >
> >
> >Aurelian Lazarut wrote:
> >
> >
> >>Methi,
> >>Can you post the error message from Map?
> >>Aurash
> >>methi wrote:
> >>
> >>
> >>
> >>>Hi..
> >>>I am currently working with Xilinx ISE 6.3i ..The design is in
> >>>
> >>>
> >VHDL..I
> >
> >
> >>>tried adding some extra inputs and outputs to the top level entity
> >>>
> >>>
> >and
> >
> >
> >>>hence made the corresponding changes to the UCF file.
> >>>But when I try implementing the design, it shows errors in the Map
> >>>process as follows:
> >>>1) The extra inputs I added in the UCF file are shown as invalid
> >>>
> >>>I have just used the format
> >>>
> >>>for example:
> >>>
> >>>NET "my_input_name"  LOC = "P34" ;
> >>>
> >>>2)Should I also add INST?
> >>>
> >>>If so how should I do that and is it for all the component
> >>>instantiations?
> >>>
> >>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
> >>>
> >>>I then removed the unused inputs and outputs but it still shows

the

> >>>same error...
> >>>
> >>>Any suggestions are welcome..
> >>>
> >>>Thanks in advance,
> >>>
> >>>Methi
> >>>
> >>>
> >>>
> >>>
> >>>
> >>--
> >> __
> >>/ /\/\ Aurelian Lazarut
> >>\ \  / System Verification Engineer
> >>/ /  \ Xilinx Ireland
> >>\_\/\/
> >>
> >>phone:	353 01 4032639
> >>fax:	353 01 4640324
> >>
> >>
> >
> >
> >
>
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324
Reply by Aurelian Lazarut ●May 24, 20052005-05-24
Did you insert IOs when you synthesized the design (It could be the case 
that tou dont have IBUFs OBUFS or IOBUFS connecting the actual signal 
with your IO pad) ???or the mapper took out all your IO due to clock 
missing (or constant in your HDL (trim out all your IOs) check the 
detailed map report which shows all the signals optimised out.
Aurash
methi wrote:


>Hi Aurash and Sean..
>
>Thanks for helping me out..
>
>I am using XC3S400_4TQ144....
>
>There are totally 144 pins...
>
>And the connections have been made on the board..but the FPGA isnt
>programmed as yet...
>
>Thats what I was trying to do...program it...give the same pins to the
>variables in the UCF...
>
>Thanks,
>Methi..
>Aurelian Lazarut wrote:
>  
>
>>what part/package are you targeting?
>>Aurash
>>methi wrote:
>>
>>    
>>
>>>Hi Aurash,
>>>
>>>These are the error messages:
>>>
>>>ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No
>>>      
>>>
>such
>  
>
>>>site on
>>>ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No
>>>      
>>>
>such
>  
>
>>>site on
>>>ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid:
>>>      
>>>
>No
>  
>
>>>such site
>>>ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
>>>site on the
>>>ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No
>>>      
>>>
>such
>  
>
>>>site on
>>>ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is
>>>      
>>>
>invalid:
>  
>
>>>No such
>>>ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No
>>>      
>>>
>such
>  
>
>>>site on
>>>ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such
>>>      
>>>
>site
>  
>
>>>on the
>>>ERROR: MAP failed
>>>
>>>Thankyou,
>>>Methi
>>>
>>>
>>>Aurelian Lazarut wrote:
>>>
>>>
>>>      
>>>
>>>>Methi,
>>>>Can you post the error message from Map?
>>>>Aurash
>>>>methi wrote:
>>>>
>>>>
>>>>
>>>>        
>>>>
>>>>>Hi..
>>>>>I am currently working with Xilinx ISE 6.3i ..The design is in
>>>>>
>>>>>
>>>>>          
>>>>>
>>>VHDL..I
>>>
>>>
>>>      
>>>
>>>>>tried adding some extra inputs and outputs to the top level entity
>>>>>
>>>>>
>>>>>          
>>>>>
>>>and
>>>
>>>
>>>      
>>>
>>>>>hence made the corresponding changes to the UCF file.
>>>>>But when I try implementing the design, it shows errors in the Map
>>>>>process as follows:
>>>>>1) The extra inputs I added in the UCF file are shown as invalid
>>>>>
>>>>>I have just used the format
>>>>>
>>>>>for example:
>>>>>
>>>>>NET "my_input_name"  LOC = "P34" ;
>>>>>
>>>>>2)Should I also add INST?
>>>>>
>>>>>If so how should I do that and is it for all the component
>>>>>instantiations?
>>>>>
>>>>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
>>>>>
>>>>>I then removed the unused inputs and outputs but it still shows
>>>>>          
>>>>>
>the
>  
>
>>>>>same error...
>>>>>
>>>>>Any suggestions are welcome..
>>>>>
>>>>>Thanks in advance,
>>>>>
>>>>>Methi
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>          
>>>>>
>>>>--
>>>>__
>>>>/ /\/\ Aurelian Lazarut
>>>>\ \  / System Verification Engineer
>>>>/ /  \ Xilinx Ireland
>>>>\_\/\/
>>>>
>>>>phone:	353 01 4032639
>>>>fax:	353 01 4640324
>>>>
>>>>
>>>>        
>>>>
>>>
>>>      
>>>
>>--
>> __
>>/ /\/\ Aurelian Lazarut
>>\ \  / System Verification Engineer
>>/ /  \ Xilinx Ireland
>>\_\/\/
>> 
>>phone:	353 01 4032639
>>fax:	353 01 4640324
>>    
>>
>
>  
>



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply by methi ●May 24, 20052005-05-24
Hi Aurash,

My Map report is as follows:

It doesnt show any removed signals..

How do I insert IO's when I synthesize the design?...Do u mean include
them in the code?...If so , yes I have included them in the code(top
level entity)...


------------------
Release 6.3.02i Map G.37
Xilinx Mapping Report File for Design 'top_1190_mem'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p
xc2s200e-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd top_1190_mem.ngd
top_1190_mem.pcf
Target Device  : x2s200e
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2e -- $Revision: 1.16.8.2 $
Mapped Date    : Mon May 23 17:19:17 2005

Design Summary
--------------
Number of errors   :  21
Number of warnings :   0

Section 1 - Errors
------------------
ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such
site on
   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such
site on
   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid: No
such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
site on the
   device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such
site on
   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is invalid:
No such
   site on the device. To bypass this error set the environment
variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such
site on
   the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site
on the
   device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------





This is wat the Map report shows.....

Thanks,
Methi


Aurelian Lazarut wrote:

> Did you insert IOs when you synthesized the design (It could be the

case

> that tou dont have IBUFs OBUFS or IOBUFS connecting the actual signal



> with your IO pad) ???or the mapper took out all your IO due to clock
> missing (or constant in your HDL (trim out all your IOs) check the
> detailed map report which shows all the signals optimised out.
> Aurash
> methi wrote:
>
> >Hi Aurash and Sean..
> >
> >Thanks for helping me out..
> >
> >I am using XC3S400_4TQ144....
> >
> >There are totally 144 pins...
> >
> >And the connections have been made on the board..but the FPGA isnt
> >programmed as yet...
> >
> >Thats what I was trying to do...program it...give the same pins to

the

> >variables in the UCF...
> >
> >Thanks,
> >Methi..
> >Aurelian Lazarut wrote:
> >
> >
> >>what part/package are you targeting?
> >>Aurash
> >>methi wrote:
> >>
> >>
> >>
> >>>Hi Aurash,
> >>>
> >>>These are the error messages:
> >>>
> >>>ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No
> >>>
> >>>
> >such
> >
> >
> >>>site on
> >>>ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No
> >>>
> >>>
> >such
> >
> >
> >>>site on
> >>>ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is

invalid:

> >>>
> >>>
> >No
> >
> >
> >>>such site
> >>>ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No

such

> >>>site on the
> >>>ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No
> >>>
> >>>
> >such
> >
> >
> >>>site on
> >>>ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is
> >>>
> >>>
> >invalid:
> >
> >
> >>>No such
> >>>ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No
> >>>
> >>>
> >such
> >
> >
> >>>site on
> >>>ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such
> >>>
> >>>
> >site
> >
> >
> >>>on the
> >>>ERROR: MAP failed
> >>>
> >>>Thankyou,
> >>>Methi
> >>>
> >>>
> >>>Aurelian Lazarut wrote:
> >>>
> >>>
> >>>
> >>>
> >>>>Methi,
> >>>>Can you post the error message from Map?
> >>>>Aurash
> >>>>methi wrote:
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>>Hi..
> >>>>>I am currently working with Xilinx ISE 6.3i ..The design is in
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>VHDL..I
> >>>
> >>>
> >>>
> >>>
> >>>>>tried adding some extra inputs and outputs to the top level

entity

> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>and
> >>>
> >>>
> >>>
> >>>
> >>>>>hence made the corresponding changes to the UCF file.
> >>>>>But when I try implementing the design, it shows errors in the

Map

> >>>>>process as follows:
> >>>>>1) The extra inputs I added in the UCF file are shown as invalid
> >>>>>
> >>>>>I have just used the format
> >>>>>
> >>>>>for example:
> >>>>>
> >>>>>NET "my_input_name"  LOC = "P34" ;
> >>>>>
> >>>>>2)Should I also add INST?
> >>>>>
> >>>>>If so how should I do that and is it for all the component
> >>>>>instantiations?
> >>>>>
> >>>>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
> >>>>>
> >>>>>I then removed the unused inputs and outputs but it still shows
> >>>>>
> >>>>>
> >the
> >
> >
> >>>>>same error...
> >>>>>
> >>>>>Any suggestions are welcome..
> >>>>>
> >>>>>Thanks in advance,
> >>>>>
> >>>>>Methi
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>--
> >>>>__
> >>>>/ /\/\ Aurelian Lazarut
> >>>>\ \  / System Verification Engineer
> >>>>/ /  \ Xilinx Ireland
> >>>>\_\/\/
> >>>>
> >>>>phone:	353 01 4032639
> >>>>fax:	353 01 4640324
> >>>>
> >>>>
> >>>>
> >>>>
> >>>
> >>>
> >>>
> >>--
> >> __
> >>/ /\/\ Aurelian Lazarut
> >>\ \  / System Verification Engineer
> >>/ /  \ Xilinx Ireland
> >>\_\/\/
> >>
> >>phone:	353 01 4032639
> >>fax:	353 01 4640324
> >>
> >>
> >
> >
> >
>
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324
Reply by Yttrium ●May 24, 20052005-05-24
are the pin names correct? because i thought in S3 they use a letter/number
assignment and not p/nimber?


"methi" <gmethi@gmail.com> wrote in message
news:1116950657.119411.64660@z14g2000cwz.googlegroups.com...

>
> Hi Aurash,
>
> My Map report is as follows:
>
> It doesnt show any removed signals..
>
> How do I insert IO's when I synthesize the design?...Do u mean include
> them in the code?...If so , yes I have included them in the code(top
> level entity)...
>
>
> ------------------
> Release 6.3.02i Map G.37
> Xilinx Mapping Report File for Design 'top_1190_mem'
>
> Design Information
> ------------------
> Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p
> xc2s200e-pq208-6 -cm
> area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd top_1190_mem.ngd
> top_1190_mem.pcf
> Target Device  : x2s200e
> Target Package : pq208
> Target Speed   : -6
> Mapper Version : spartan2e -- $Revision: 1.16.8.2 $
> Mapped Date    : Mon May 23 17:19:17 2005
>
> Design Summary
> --------------
> Number of errors   :  21
> Number of warnings :   0
>
> Section 1 - Errors
> ------------------
> ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such
> site on
>    the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such
> site on
>    the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid: No
> such site
>    on the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
> site on the
>    device. To bypass this error set the environment variable
> 'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such
> site on
>    the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is invalid:
> No such
>    site on the device. To bypass this error set the environment
> variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such
> site on
>    the device. To bypass this error set the environment variable
>    'XIL_MAP_LOCWARN'.
> ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site
> on the
>    device. To bypass this error set the environment variable
> 'XIL_MAP_LOCWARN'.
>
> Section 2 - Warnings
> --------------------
>
> Section 3 - Informational
> -------------------------
> INFO:MapLib:562 - No environment variables are currently set.
>
> Section 4 - Removed Logic Summary
> ---------------------------------
>
> Section 5 - Removed Logic
> -------------------------
>
>
>
>
>
> This is wat the Map report shows.....
>
> Thanks,
> Methi
>
>
> Aurelian Lazarut wrote:
> > Did you insert IOs when you synthesized the design (It could be the
> case
> > that tou dont have IBUFs OBUFS or IOBUFS connecting the actual signal
>
> > with your IO pad) ???or the mapper took out all your IO due to clock
> > missing (or constant in your HDL (trim out all your IOs) check the
> > detailed map report which shows all the signals optimised out.
> > Aurash
> > methi wrote:
> >
> > >Hi Aurash and Sean..
> > >
> > >Thanks for helping me out..
> > >
> > >I am using XC3S400_4TQ144....
> > >
> > >There are totally 144 pins...
> > >
> > >And the connections have been made on the board..but the FPGA isnt
> > >programmed as yet...
> > >
> > >Thats what I was trying to do...program it...give the same pins to
> the
> > >variables in the UCF...
> > >
> > >Thanks,
> > >Methi..
> > >Aurelian Lazarut wrote:
> > >
> > >
> > >>what part/package are you targeting?
> > >>Aurash
> > >>methi wrote:
> > >>
> > >>
> > >>
> > >>>Hi Aurash,
> > >>>
> > >>>These are the error messages:
> > >>>
> > >>>ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No
> > >>>
> > >>>
> > >such
> > >
> > >
> > >>>site on
> > >>>ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No
> > >>>
> > >>>
> > >such
> > >
> > >
> > >>>site on
> > >>>ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is
> invalid:
> > >>>
> > >>>
> > >No
> > >
> > >
> > >>>such site
> > >>>ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No
> such
> > >>>site on the
> > >>>ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No
> > >>>
> > >>>
> > >such
> > >
> > >
> > >>>site on
> > >>>ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is
> > >>>
> > >>>
> > >invalid:
> > >
> > >
> > >>>No such
> > >>>ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No
> > >>>
> > >>>
> > >such
> > >
> > >
> > >>>site on
> > >>>ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such
> > >>>
> > >>>
> > >site
> > >
> > >
> > >>>on the
> > >>>ERROR: MAP failed
> > >>>
> > >>>Thankyou,
> > >>>Methi
> > >>>
> > >>>
> > >>>Aurelian Lazarut wrote:
> > >>>
> > >>>
> > >>>
> > >>>
> > >>>>Methi,
> > >>>>Can you post the error message from Map?
> > >>>>Aurash
> > >>>>methi wrote:
> > >>>>
> > >>>>
> > >>>>
> > >>>>
> > >>>>
> > >>>>>Hi..
> > >>>>>I am currently working with Xilinx ISE 6.3i ..The design is in
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>VHDL..I
> > >>>
> > >>>
> > >>>
> > >>>
> > >>>>>tried adding some extra inputs and outputs to the top level
> entity
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>and
> > >>>
> > >>>
> > >>>
> > >>>
> > >>>>>hence made the corresponding changes to the UCF file.
> > >>>>>But when I try implementing the design, it shows errors in the
> Map
> > >>>>>process as follows:
> > >>>>>1) The extra inputs I added in the UCF file are shown as invalid
> > >>>>>
> > >>>>>I have just used the format
> > >>>>>
> > >>>>>for example:
> > >>>>>
> > >>>>>NET "my_input_name"  LOC = "P34" ;
> > >>>>>
> > >>>>>2)Should I also add INST?
> > >>>>>
> > >>>>>If so how should I do that and is it for all the component
> > >>>>>instantiations?
> > >>>>>
> > >>>>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
> > >>>>>
> > >>>>>I then removed the unused inputs and outputs but it still shows
> > >>>>>
> > >>>>>
> > >the
> > >
> > >
> > >>>>>same error...
> > >>>>>
> > >>>>>Any suggestions are welcome..
> > >>>>>
> > >>>>>Thanks in advance,
> > >>>>>
> > >>>>>Methi
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>--
> > >>>>__
> > >>>>/ /\/\ Aurelian Lazarut
> > >>>>\ \  / System Verification Engineer
> > >>>>/ /  \ Xilinx Ireland
> > >>>>\_\/\/
> > >>>>
> > >>>>phone: 353 01 4032639
> > >>>>fax: 353 01 4640324
> > >>>>
> > >>>>
> > >>>>
> > >>>>
> > >>>
> > >>>
> > >>>
> > >>--
> > >> __
> > >>/ /\/\ Aurelian Lazarut
> > >>\ \  / System Verification Engineer
> > >>/ /  \ Xilinx Ireland
> > >>\_\/\/
> > >>
> > >>phone: 353 01 4032639
> > >>fax: 353 01 4640324
> > >>
> > >>
> > >
> > >
> > >
> >
> >
> > --
> >  __
> > / /\/\ Aurelian Lazarut
> > \ \  / System Verification Engineer
> > / /  \ Xilinx Ireland
> > \_\/\/
> >
> > phone: 353 01 4032639
> > fax: 353 01 4640324
>
Reply by methi ●May 24, 20052005-05-24
Hi..

This is the way I have written the assignment in the UCF file..not sure
if this is correct:

for example:

NET "dig_video_out<8>"  LOC = "P113" | IOSTANDARD = LVTTL ;
NET "dig_video_out<9>"  LOC = "P112" | IOSTANDARD = LVTTL ;
NET "dqm<0>"  LOC = "P26" | IOSTANDARD = LVTTL  | SLEW = FAST ;
NET "dqm<1>"  LOC = "P27" | IOSTANDARD = LVTTL  | SLEW = FAST ;
NET "pal_ntsc"  LOC = "P77" | IOSTANDARD = LVTTL ;
NET "probe"  LOC = "p78"  ;
NET "ref_27mhz"  LOC = "P53" | IOSTANDARD = LVTTL ;
NET "sd_clk"  LOC = "P30" | IOSTANDARD = LVTTL  | SLEW = FAST ;
NET "sd_clk_en"  LOC = "P32"  ;
NET "sd_cs"  LOC = "P35"  ;
NET "sd_ram_address<0>"  LOC = "P60" | IOSTANDARD = LVTTL  | SLEW =
FAST  | PULLUP ;


I havent written anything about the component instantiations...

Thanks,
Methi
Yttrium wrote:

> are the pin names correct? because i thought in S3 they use a

letter/number

> assignment and not p/nimber?
>
>
> "methi" <gmethi@gmail.com> wrote in message
> news:1116950657.119411.64660@z14g2000cwz.googlegroups.com...
> >
> > Hi Aurash,
> >
> > My Map report is as follows:
> >
> > It doesnt show any removed signals..
> >
> > How do I insert IO's when I synthesize the design?...Do u mean

include

> > them in the code?...If so , yes I have included them in the

code(top

> > level entity)...
> >
> >
> > ------------------
> > Release 6.3.02i Map G.37
> > Xilinx Mapping Report File for Design 'top_1190_mem'
> >
> > Design Information
> > ------------------
> > Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p
> > xc2s200e-pq208-6 -cm
> > area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd

top_1190_mem.ngd

> > top_1190_mem.pcf
> > Target Device  : x2s200e
> > Target Package : pq208
> > Target Speed   : -6
> > Mapper Version : spartan2e -- $Revision: 1.16.8.2 $
> > Mapped Date    : Mon May 23 17:19:17 2005
> >
> > Design Summary
> > --------------
> > Number of errors   :  21
> > Number of warnings :   0
> >
> > Section 1 - Errors
> > ------------------
> > ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No

such

> > site on
> >    the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No

such

> > site on
> >    the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is invalid:

No

> > such site
> >    on the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No such
> > site on the
> >    device. To bypass this error set the environment variable
> > 'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No

such

> > site on
> >    the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is

invalid:

> > No such
> >    site on the device. To bypass this error set the environment
> > variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No

such

> > site on
> >    the device. To bypass this error set the environment variable
> >    'XIL_MAP_LOCWARN'.
> > ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such

site

> > on the
> >    device. To bypass this error set the environment variable
> > 'XIL_MAP_LOCWARN'.
> >
> > Section 2 - Warnings
> > --------------------
> >
> > Section 3 - Informational
> > -------------------------
> > INFO:MapLib:562 - No environment variables are currently set.
> >
> > Section 4 - Removed Logic Summary
> > ---------------------------------
> >
> > Section 5 - Removed Logic
> > -------------------------
> >
> >
> >
> >
> >
> > This is wat the Map report shows.....
> >
> > Thanks,
> > Methi
> >
> >
> > Aurelian Lazarut wrote:
> > > Did you insert IOs when you synthesized the design (It could be

the

> > case
> > > that tou dont have IBUFs OBUFS or IOBUFS connecting the actual

signal

> >
> > > with your IO pad) ???or the mapper took out all your IO due to

clock

> > > missing (or constant in your HDL (trim out all your IOs) check

the

> > > detailed map report which shows all the signals optimised out.
> > > Aurash
> > > methi wrote:
> > >
> > > >Hi Aurash and Sean..
> > > >
> > > >Thanks for helping me out..
> > > >
> > > >I am using XC3S400_4TQ144....
> > > >
> > > >There are totally 144 pins...
> > > >
> > > >And the connections have been made on the board..but the FPGA

isnt

> > > >programmed as yet...
> > > >
> > > >Thats what I was trying to do...program it...give the same pins

to

> > the
> > > >variables in the UCF...
> > > >
> > > >Thanks,
> > > >Methi..
> > > >Aurelian Lazarut wrote:
> > > >
> > > >
> > > >>what part/package are you targeting?
> > > >>Aurash
> > > >>methi wrote:
> > > >>
> > > >>
> > > >>
> > > >>>Hi Aurash,
> > > >>>
> > > >>>These are the error messages:
> > > >>>
> > > >>>ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid:

No

> > > >>>
> > > >>>
> > > >such
> > > >
> > > >
> > > >>>site on
> > > >>>ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid:

No

> > > >>>
> > > >>>
> > > >such
> > > >
> > > >
> > > >>>site on
> > > >>>ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data<19> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data<18> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data<8> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data<7> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data<6> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data<5> is
> > invalid:
> > > >>>
> > > >>>
> > > >No
> > > >
> > > >
> > > >>>such site
> > > >>>ERROR:MapLib:681 - LOC constraint P119 on dig_video_out<6> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P118 on dig_video_out<7> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P130 on dig_video_out<3> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P26 on dqm<0> is invalid: No
> > such
> > > >>>site on the
> > > >>>ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address<5> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address<4> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P131 on dig_video_out<2> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P128 on reset_bar is

invalid: No

> > > >>>
> > > >>>
> > > >such
> > > >
> > > >
> > > >>>site on
> > > >>>ERROR:MapLib:681 - LOC constraint P103 on dig_video_in<4> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P104 on dig_video_in<3> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P105 on dig_video_in<2> is
> > > >>>
> > > >>>
> > > >invalid:
> > > >
> > > >
> > > >>>No such
> > > >>>ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid:

No

> > > >>>
> > > >>>
> > > >such
> > > >
> > > >
> > > >>>site on
> > > >>>ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No

such

> > > >>>
> > > >>>
> > > >site
> > > >
> > > >
> > > >>>on the
> > > >>>ERROR: MAP failed
> > > >>>
> > > >>>Thankyou,
> > > >>>Methi
> > > >>>
> > > >>>
> > > >>>Aurelian Lazarut wrote:
> > > >>>
> > > >>>
> > > >>>
> > > >>>
> > > >>>>Methi,
> > > >>>>Can you post the error message from Map?
> > > >>>>Aurash
> > > >>>>methi wrote:
> > > >>>>
> > > >>>>
> > > >>>>
> > > >>>>
> > > >>>>
> > > >>>>>Hi..
> > > >>>>>I am currently working with Xilinx ISE 6.3i ..The design is

in

> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>VHDL..I
> > > >>>
> > > >>>
> > > >>>
> > > >>>
> > > >>>>>tried adding some extra inputs and outputs to the top level
> > entity
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>and
> > > >>>
> > > >>>
> > > >>>
> > > >>>
> > > >>>>>hence made the corresponding changes to the UCF file.
> > > >>>>>But when I try implementing the design, it shows errors in

the

> > Map
> > > >>>>>process as follows:
> > > >>>>>1) The extra inputs I added in the UCF file are shown as

invalid

> > > >>>>>
> > > >>>>>I have just used the format
> > > >>>>>
> > > >>>>>for example:
> > > >>>>>
> > > >>>>>NET "my_input_name"  LOC = "P34" ;
> > > >>>>>
> > > >>>>>2)Should I also add INST?
> > > >>>>>
> > > >>>>>If so how should I do that and is it for all the component
> > > >>>>>instantiations?
> > > >>>>>
> > > >>>>>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
> > > >>>>>
> > > >>>>>I then removed the unused inputs and outputs but it still

shows

> > > >>>>>
> > > >>>>>
> > > >the
> > > >
> > > >
> > > >>>>>same error...
> > > >>>>>
> > > >>>>>Any suggestions are welcome..
> > > >>>>>
> > > >>>>>Thanks in advance,
> > > >>>>>
> > > >>>>>Methi
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>>
> > > >>>>--
> > > >>>>__
> > > >>>>/ /\/\ Aurelian Lazarut
> > > >>>>\ \  / System Verification Engineer
> > > >>>>/ /  \ Xilinx Ireland
> > > >>>>\_\/\/
> > > >>>>
> > > >>>>phone: 353 01 4032639
> > > >>>>fax: 353 01 4640324
> > > >>>>
> > > >>>>
> > > >>>>
> > > >>>>
> > > >>>
> > > >>>
> > > >>>
> > > >>--
> > > >> __
> > > >>/ /\/\ Aurelian Lazarut
> > > >>\ \  / System Verification Engineer
> > > >>/ /  \ Xilinx Ireland
> > > >>\_\/\/
> > > >>
> > > >>phone: 353 01 4032639
> > > >>fax: 353 01 4640324
> > > >>
> > > >>
> > > >
> > > >
> > > >
> > >
> > >
> > > --
> > >  __
> > > / /\/\ Aurelian Lazarut
> > > \ \  / System Verification Engineer
> > > / /  \ Xilinx Ireland
> > > \_\/\/
> > >
> > > phone: 353 01 4032639
> > > fax: 353 01 4640324
> >